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doctoral thesis
Nova arhitektura nabojske pumpe s Fibonaccijevim stupnjem
Osijek: Josip Juraj Strossmayer University of Osijek, Faculty of Electrical Engineering, Computer Science and Information Technology Osijek, 2012. urn:nbn:hr:200:830279
Vinko, Davor
Josip Juraj Strossmayer University of Osijek
Faculty of Electrical Engineering, Computer Science and Information Technology Osijek
Department of Communications
Chair of Electronics and Microelectronics

Institutional repository: Faculty of Electrical Engineering, Computer Science and Information Technology Osijek

Cite this document

Vinko, D. (2012). Nova arhitektura nabojske pumpe s Fibonaccijevim stupnjem (Doctoral thesis). Osijek: Josip Juraj Strossmayer University of Osijek, Faculty of Electrical Engineering, Computer Science and Information Technology Osijek. Retrieved from https://urn.nsk.hr/urn:nbn:hr:200:830279

Vinko, Davor. "Nova arhitektura nabojske pumpe s Fibonaccijevim stupnjem." Doctoral thesis, Josip Juraj Strossmayer University of Osijek, Faculty of Electrical Engineering, Computer Science and Information Technology Osijek, 2012. https://urn.nsk.hr/urn:nbn:hr:200:830279

Vinko, Davor. "Nova arhitektura nabojske pumpe s Fibonaccijevim stupnjem." Doctoral thesis, Josip Juraj Strossmayer University of Osijek, Faculty of Electrical Engineering, Computer Science and Information Technology Osijek, 2012. https://urn.nsk.hr/urn:nbn:hr:200:830279

Vinko, D. (2012). 'Nova arhitektura nabojske pumpe s Fibonaccijevim stupnjem', Doctoral thesis, Josip Juraj Strossmayer University of Osijek, Faculty of Electrical Engineering, Computer Science and Information Technology Osijek, accessed 27 November 2024, https://urn.nsk.hr/urn:nbn:hr:200:830279

Vinko D. Nova arhitektura nabojske pumpe s Fibonaccijevim stupnjem [Doctoral thesis]. Osijek: Josip Juraj Strossmayer University of Osijek, Faculty of Electrical Engineering, Computer Science and Information Technology Osijek; 2012 [cited 2024 November 27] Available at: https://urn.nsk.hr/urn:nbn:hr:200:830279

D. Vinko, "Nova arhitektura nabojske pumpe s Fibonaccijevim stupnjem", Doctoral thesis, Josip Juraj Strossmayer University of Osijek, Faculty of Electrical Engineering, Computer Science and Information Technology Osijek, Osijek, 2012. Available at: https://urn.nsk.hr/urn:nbn:hr:200:830279

Metadata
TitleNova arhitektura nabojske pumpe s Fibonaccijevim stupnjem
Title (english)Novel charge pump architecture with Fibonacci stage
AuthorDavor Vinko
MentorTomislav Švedek (mentor)
Committee memberTomislav Matić (predsjednik povjerenstva)
GranterJosip Juraj Strossmayer University of Osijek
Faculty of Electrical Engineering, Computer Science and Information Technology Osijek
(Department of Communications)
(Chair of Electronics and Microelectronics)
Osijek
Defense date and country2012-07-05, Croatia
Scientific / art field,
discipline and subdiscipline		TECHNICAL SCIENCES
Electrical Engineering
Electronics
Universal decimal classification
(UDC)		621.3 - Electrical engineering
Abstract
U ovoj je doktorskoj disertaciji predstavljena nova arhitektura nabojske pumpe. U prvom dijelu rada opisan je osnovni princip rada najčešće korištene nabojske pumpe, Dicksonove nabojske pumpe, te razvijen njen novi matematički model. Novi matematički model je primjenjiv na bilo koju dvo faznu nabojsku pumpu i od postojećih se razlikuje po tome što uzima u obzir utjecaj otpora kanala tranzistora i izvora. Na osnovu predstavljenog matematičkog modela, predložena je nova metoda za određivanje parametara nabojske pumpe, koja također uzima u obzir otpor kanala tranzistora i otpor izvora, te je generalizirana tako da odgovara bilo kojoj dvo faznoj nabojskoj pumpi. Nabojske pumpe visokog dobitka, koje su u posljednje vrijeme postale popularne, također se mogu opisati predstavljenim matematičkim modelom i predloženom metodom određivanja parametara, ako koriste dva protufazna signala takta. Nakon teorijskih i matematičkih analiza, koje uključuju i utjecaj efekta podloge na napon praga tranzistora, predložena je nova arhitektura nabojske pumpe s Fibonaccijevim stupnjem. Proces projektiranja integriranog CMOS sklopa u Cadence okruženju je detaljno opisan i prikazani su rezultati simulacije sa i bez ekstrahiranih paratiznih parametara. Korištenjem Fibonaccijevom stupnja dobiveni su viši izlazni naponi od izlaznih napona klasičnih arhitektura nabojskih pumpi, a CVSL sklop je dokazan kao jednostavno i efikasno rješenje za ispravno upravljanje Fibonaccijevim stupnjem. Nova arhitektura nabojske pumpe je procesirana u sklopu testnog integriranog sklopa korištenjem 0,35 μm AMS-ovog C35B4C3 tehnološkog procesa, zajedno s Dicksonovom, CTS i modificiranom CTS nabojskom pumpom koje služe za usporedbu s novom arhitekturom. Rezultati mjerenja su uspoređeni s rezultatima simulacije, a njihova međusobna odstupanja su detaljno objašnjena. Na temelju usporedbe mjernih i simulacijskih rezultata, dokazano je da SPICE model netočno modelira rad tranzistora u području ispon napona praga te time i ponašanje nabojske pumpe za čisto kapacitivna opterećenja. Također, utvrđeno je formiranje niskopropusnog filtra na priključcima signala takta kod testnog integriranog sklopa, te su predložene metode za rješavanje tog problema.
Abstract (english)
In this doctoral thesis a novel charge pump architecture is presented. In the first part of the thesis the basic principles of operation of the most common charge pump, Dickson charge pump, are described and a novel mathematical model is developed and presented. The presented model is appliable to any two-phase charge pump and it takes into account resistance of MOSFET switches and the power supply resistance as well. Based on the presented mathematical model, a new method for charge pump parameter determination is proposed, which also takes into account the switch and the power supply resistance, and it is generalized to correspond to any two-phase charge pump. Recent high gain charge pump designs, as long as they are two-phase designs, can also be descibed with presented mathematical model and proposed method. After theoretical and mathematical analysis, including body effect on the threshold voltage of the NMOS devices, a novel charge pump architecture with Fibonacci stage is presented. Designing process in Cadence environment is explained in detail and simulation results, both with and without exctracted parasitics, are given. The higher output voltages of the novel architecture, compared with common charge pump architectures, due to used Fibonacci stage are observed and the CVSL circuit is proven to be simple and efficient solution for high amplitude clock generator that is needed to drive the Fibonacci stage. The novel charge pump is proccessed in integrated circuit using 0,35 µm AMS C35B4C3 technology process, together with Dickson, CTS and modified CTS charge pump which are used for comparison with new architecture. Measurements of the fabricated charge pumps are compared with simulation results and the discrepancies are explained. Based on the measurement and simulation comparison, the SPICE model behavior in subthreshold region for a charge pump operating under capacitive load is proved to be faulty. Also, the forming of the low-pass filter on the clock signal pins in processed and bonded integrated circuit is determined, and some solutions are proposed.
Keywords
Keywords (english)
Languagecroatian
URN:NBNurn:nbn:hr:200:830279
Promotion2012-07-05
Study programmeTitle: Postgraduate doctoral study programme; specializations in: branch Power Engineering and Communications, branch Informatics
Course: branch Power Engineering and Communications
Study programme type: university
Study level: postgraduate
Academic / professional title: doktor/doktorica znanosti, područje tehničkih znanosti, polje elektrotehnika (doktor/doktorica znanosti, područje tehničkih znanosti, polje elektrotehnika)
Type of resourceText
File originBorn digital
Access conditionsOpen access
Terms of useLicence In copyright icon
Created on2018-03-07 15:12:47