Implementacija modulacije prostornog vektora na CRIO FPGA platformi
Osijek: Josip Juraj Strossmayer University of Osijek, Faculty of Electrical Engineering, Computer Science and Information Technology Osijek, 2018. urn:nbn:hr:200:169966
Ugljar, Marjan
Josip Juraj Strossmayer University of Osijek Faculty of Electrical Engineering, Computer Science and Information Technology Osijek Department of Electromechanical Engineering Chair of Fundamentals of Electrical Engineering and Measurements
Ugljar, M. (2018). Implementacija modulacije prostornog vektora na CRIO FPGA platformi (Master's thesis). Osijek: Josip Juraj Strossmayer University of Osijek, Faculty of Electrical Engineering, Computer Science and Information Technology Osijek. Retrieved from https://urn.nsk.hr/urn:nbn:hr:200:169966
Ugljar, Marjan. "Implementacija modulacije prostornog vektora na CRIO FPGA platformi." Master's thesis, Josip Juraj Strossmayer University of Osijek, Faculty of Electrical Engineering, Computer Science and Information Technology Osijek, 2018. https://urn.nsk.hr/urn:nbn:hr:200:169966
Ugljar, Marjan. "Implementacija modulacije prostornog vektora na CRIO FPGA platformi." Master's thesis, Josip Juraj Strossmayer University of Osijek, Faculty of Electrical Engineering, Computer Science and Information Technology Osijek, 2018. https://urn.nsk.hr/urn:nbn:hr:200:169966
Ugljar, M. (2018). 'Implementacija modulacije prostornog vektora na CRIO FPGA platformi', Master's thesis, Josip Juraj Strossmayer University of Osijek, Faculty of Electrical Engineering, Computer Science and Information Technology Osijek, accessed 11 October 2024, https://urn.nsk.hr/urn:nbn:hr:200:169966
Ugljar M. Implementacija modulacije prostornog vektora na CRIO FPGA platformi [Master's thesis]. Osijek: Josip Juraj Strossmayer University of Osijek, Faculty of Electrical Engineering, Computer Science and Information Technology Osijek; 2018 [cited 2024 October 11] Available at: https://urn.nsk.hr/urn:nbn:hr:200:169966
M. Ugljar, "Implementacija modulacije prostornog vektora na CRIO FPGA platformi", Master's thesis, Josip Juraj Strossmayer University of Osijek, Faculty of Electrical Engineering, Computer Science and Information Technology Osijek, Osijek, 2018. Available at: https://urn.nsk.hr/urn:nbn:hr:200:169966