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master's thesis
Snimanje i reprodukcija video signala uz podršku za više kamera zasnovano na FPGA
Osijek: Josip Juraj Strossmayer University of Osijek, Faculty of Electrical Engineering, Computer Science and Information Technology Osijek, 2018. urn:nbn:hr:200:429286
Vido, Ivan
Josip Juraj Strossmayer University of Osijek
Faculty of Electrical Engineering, Computer Science and Information Technology Osijek
Department of Communications
Chair of Electronics and Microelectronics

Institutional repository: Faculty of Electrical Engineering, Computer Science and Information Technology Osijek

Cite this document

Vido, I. (2018). Snimanje i reprodukcija video signala uz podršku za više kamera zasnovano na FPGA (Master's thesis). Osijek: Josip Juraj Strossmayer University of Osijek, Faculty of Electrical Engineering, Computer Science and Information Technology Osijek. Retrieved from https://urn.nsk.hr/urn:nbn:hr:200:429286

Vido, Ivan. "Snimanje i reprodukcija video signala uz podršku za više kamera zasnovano na FPGA." Master's thesis, Josip Juraj Strossmayer University of Osijek, Faculty of Electrical Engineering, Computer Science and Information Technology Osijek, 2018. https://urn.nsk.hr/urn:nbn:hr:200:429286

Vido, Ivan. "Snimanje i reprodukcija video signala uz podršku za više kamera zasnovano na FPGA." Master's thesis, Josip Juraj Strossmayer University of Osijek, Faculty of Electrical Engineering, Computer Science and Information Technology Osijek, 2018. https://urn.nsk.hr/urn:nbn:hr:200:429286

Vido, I. (2018). 'Snimanje i reprodukcija video signala uz podršku za više kamera zasnovano na FPGA', Master's thesis, Josip Juraj Strossmayer University of Osijek, Faculty of Electrical Engineering, Computer Science and Information Technology Osijek, accessed 20 May 2024, https://urn.nsk.hr/urn:nbn:hr:200:429286

Vido I. Snimanje i reprodukcija video signala uz podršku za više kamera zasnovano na FPGA [Master's thesis]. Osijek: Josip Juraj Strossmayer University of Osijek, Faculty of Electrical Engineering, Computer Science and Information Technology Osijek; 2018 [cited 2024 May 20] Available at: https://urn.nsk.hr/urn:nbn:hr:200:429286

I. Vido, "Snimanje i reprodukcija video signala uz podršku za više kamera zasnovano na FPGA", Master's thesis, Josip Juraj Strossmayer University of Osijek, Faculty of Electrical Engineering, Computer Science and Information Technology Osijek, Osijek, 2018. Available at: https://urn.nsk.hr/urn:nbn:hr:200:429286

Metadata
TitleSnimanje i reprodukcija video signala uz podršku za više kamera zasnovano na FPGA
Title (english)Recording and playback of video signals with support for multiple cameras based on FPGAs
AuthorIvan Vido
MentorMarijan Herceg (mentor)
Committee memberMarijan Herceg (predsjednik povjerenstva)
Committee memberRatko Grbić (član povjerenstva)
Committee memberMario Vranješ (član povjerenstva)
GranterJosip Juraj Strossmayer University of Osijek
Faculty of Electrical Engineering, Computer Science and Information Technology Osijek
(Department of Communications)
(Chair of Electronics and Microelectronics)
Osijek
Defense date and country2018-09-27, Croatia
Scientific / art field,
discipline and subdiscipline		TECHNICAL SCIENCES
Electrical Engineering
Telecommunications and Informatics
Abstract
Zadatak ovog diplomskog rada je napraviti FPGA dizajn koji omogućava AMV Grabber ploči primanje i zapisivanje podataka s kamera, te slanje već snimljenog video sadržaja na izlazne portove. AMV Grabber ploča ima ulogu produžetka ADAS (engl. Advanced Driver Assistance System) uređaja, jer AMV Grabber omogućava lakši razvoj i testiranje ADAS algoritama. Dizajniranje je odrađeno u Xilinx®-ovom okruženju Vivado®, te su korišteni službeni IP blokovi koje regulira Xilinx®. Rješenje je razdvojeno na dva dijela, putanja snimanja i putanja reprodukcije iz razloga što nije bilo moguće putanju reprodukcije implementirati u kompletan projekt. Omogućeno je snimanje do devet kamera, iako hardverska ograničenja nisu dozvoljavala dovoljan protok podataka, usko grlo se pojavilo pri zapisivanju podataka na tvrdi disk. Putanja reprodukcije je razvijena zasebno i potvrda njene funkcionalnosti zahtijevala je pozamašna testiranja. Ispostavilo se da je slanje moguće, uz mali gubitak pet početnih okvira koje je nemoguće sačuvati jer su potrebni za sinkronizaciju blokova u dizajnu reprodukcije.
Abstract (english)
The purpose of this master thesis is to create an FPGA design, which allows capturing data from cameras, and reproduction of already captured data to the output ports on AMV Grabber device. AMV Grabber device acts as an extension of ADAS (Advanced Driver Assistance Systems) which allows easier development and testing of ADAS algorithms. The design has been made in Vivavo® design suite by Xilinx®. For the purposes of the design official IPs have been used. Developed design is separated into two parts, input path, and output path, because output path was not possible to implement into the complete project. Input path is able to record with up to nine cameras, even though only theoretically. Actual capabilities were the recording with five cameras because there happened to be a data flow bottle neck when writing on the SSD drive, and no AMV Grabber device had all nine input ports functional. Output path was developed on its own, so the verification of requested behavior was extensive. The final result was successful reproduction of test data with first five frame loss, due to synchronization process of the IPs used in the output design.
Keywords
Keywords (english)
Languagecroatian
URN:NBNurn:nbn:hr:200:429286
Study programmeTitle: Graduate University Study Programme in Electrical Engineering; specializations in: Communications and Informatics, Power Engineering
Course: Communications and Informatics
Study programme type: university
Study level: graduate
Academic / professional title: magistar/magistra inženjer/inženjerka elektrotehnike (magistar/magistra inženjer/inženjerka elektrotehnike)
Type of resourceText
File originBorn digital
Access conditionsOpen access
Terms of useLicence In copyright icon
Created on2018-10-04 15:47:46