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undergraduate thesis
FPGA IMPLEMENTACIJA 12-BITOVNOG PROCESORA ZASNOVANOG NA HARVARDSKOJ ARHITEKTURI
Osijek: Josip Juraj Strossmayer University of Osijek, Faculty of Electrical Engineering, Computer Science and Information Technology Osijek, 2019. urn:nbn:hr:200:911721
Štajnbrikner, Matej
Josip Juraj Strossmayer University of Osijek
Faculty of Electrical Engineering, Computer Science and Information Technology Osijek
Department of Computer Engineering and Automation
Chair of Automation and Robotics

Institutional repository: Faculty of Electrical Engineering, Computer Science and Information Technology Osijek

Cite this document

Štajnbrikner, M. (2019). FPGA IMPLEMENTACIJA 12-BITOVNOG PROCESORA ZASNOVANOG NA HARVARDSKOJ ARHITEKTURI (Undergraduate thesis). Osijek: Josip Juraj Strossmayer University of Osijek, Faculty of Electrical Engineering, Computer Science and Information Technology Osijek. Retrieved from https://urn.nsk.hr/urn:nbn:hr:200:911721

Štajnbrikner, Matej. "FPGA IMPLEMENTACIJA 12-BITOVNOG PROCESORA ZASNOVANOG NA HARVARDSKOJ ARHITEKTURI." Undergraduate thesis, Josip Juraj Strossmayer University of Osijek, Faculty of Electrical Engineering, Computer Science and Information Technology Osijek, 2019. https://urn.nsk.hr/urn:nbn:hr:200:911721

Štajnbrikner, Matej. "FPGA IMPLEMENTACIJA 12-BITOVNOG PROCESORA ZASNOVANOG NA HARVARDSKOJ ARHITEKTURI." Undergraduate thesis, Josip Juraj Strossmayer University of Osijek, Faculty of Electrical Engineering, Computer Science and Information Technology Osijek, 2019. https://urn.nsk.hr/urn:nbn:hr:200:911721

Štajnbrikner, M. (2019). 'FPGA IMPLEMENTACIJA 12-BITOVNOG PROCESORA ZASNOVANOG NA HARVARDSKOJ ARHITEKTURI', Undergraduate thesis, Josip Juraj Strossmayer University of Osijek, Faculty of Electrical Engineering, Computer Science and Information Technology Osijek, accessed 19 February 2025, https://urn.nsk.hr/urn:nbn:hr:200:911721

Štajnbrikner M. FPGA IMPLEMENTACIJA 12-BITOVNOG PROCESORA ZASNOVANOG NA HARVARDSKOJ ARHITEKTURI [Undergraduate thesis]. Osijek: Josip Juraj Strossmayer University of Osijek, Faculty of Electrical Engineering, Computer Science and Information Technology Osijek; 2019 [cited 2025 February 19] Available at: https://urn.nsk.hr/urn:nbn:hr:200:911721

M. Štajnbrikner, "FPGA IMPLEMENTACIJA 12-BITOVNOG PROCESORA ZASNOVANOG NA HARVARDSKOJ ARHITEKTURI", Undergraduate thesis, Josip Juraj Strossmayer University of Osijek, Faculty of Electrical Engineering, Computer Science and Information Technology Osijek, Osijek, 2019. Available at: https://urn.nsk.hr/urn:nbn:hr:200:911721

Metadata
TitleFPGA IMPLEMENTACIJA 12-BITOVNOG PROCESORA ZASNOVANOG NA HARVARDSKOJ ARHITEKTURI
Title (english)FPGA implementation of 12-bit processor based on Harvard architecture
AuthorMatej Štajnbrikner
MentorRatko Grbić (mentor)
Committee memberLeon Šneler (član povjerenstva)
GranterJosip Juraj Strossmayer University of Osijek
Faculty of Electrical Engineering, Computer Science and Information Technology Osijek
(Department of Computer Engineering and Automation)
(Chair of Automation and Robotics)
Osijek
Defense date and country2019-09-26, Croatia
Scientific / art field,
discipline and subdiscipline		TECHNICAL SCIENCES
Computing
Architecture of Computer Systems
Abstract
Cilj ovog završnog rada bio je implementirati 12-bitovni procesor temeljen na Harvardskoj arhitekturi na FPGA integrirani krug koristeći VHDL jezik za opisivanje sklopovlja, ModelSim okruženje za računalnu simulaciju, Vivado okruženje za sintezu i analizu opisanog sklopa i ZYBO razvojnu pločicu za fizičko ispitivanje valjanosti rješenja. U radu je prvo predstavljen pojam arhitekture računala kao temelj za dizajniranje procesora. Zatim je opisan VHDL i način na koji se sklopovlje opisuje u istome te ZYBO razvojna pločica i mogućnosti koje ista pruža kod fizičkog ispitivanja valjanosti rješenja. Nakon toga je opisano dizajniranje svakog dijela procesora te njegova funkcija i komunikacija s ostalim dijelovima procesora. U istom poglavlju opisana je i periferija procesora. Na kraju rada predstavljeni su alati ModelSim i Vivado koji su korišteni za verifikaciju rješenja. Dizajnirani procesor može raditi na maksimalnoj frekvenciji takta koja iznosi 80.01 MHz. Komunikacija s vanjskim uređajima odvija se pomoću UART protokola. Procesor nema mogućnost programiranja iz nekog od viših programskih jezika kao što je „C“ već se programira u strojnom kodu. Ispravnost rješenja dokazana je spajanjem ZYBO pločice na računalo preko UART sučelja i slanjem jednoznamenkastog broja s računala od kojega je procesor izračunao faktorijel i isti poslao na računalo.
Abstract (english)
The goal of this paper was to implement a 12-bit processor based on Harvard architecture on an FPGA integrated circuit using VHDL hardware description language, ModelSim environment for computer simulation, Vivado environment for synthesis and analysis of the described hardware and ZYBO development board for testing validity of the solution. Firstly, term computer architecture was introduced as a foundation for designing a processor. Secondly, the term VHDL and the way hardware is described in it were mentioned. After that, ZYBO development board and features it provides when testing validity of the solution were described. After describing ZYBO, the process of designing every part of processor, its function and communication with other parts of processor were described. In the same chapter, periphery of the processor was also described. By the end of the paper, ModelSim and Vivado were introduced for verification of the solution. The designed processor can work on a maximum frequency of 80.01 MHz. Communication with external devices is realized with UART protocol. The processor does not have the possibility to be programmed with high programming languages like “C”, but only with machine code. The correctness of the solution was proven by connecting the ZYBO board to the computer by UART interface and by sending a single-digit number from a computer to the processor. The processor calculated factorial of the number and sent it back to the computer.
Keywords
Keywords (english)
Languagecroatian
URN:NBNurn:nbn:hr:200:911721
Study programmeTitle: Undergraduate University Study Programme
Study programme type: university
Study level: undergraduate
Academic / professional title: sveučilišni/a prvostupnik/ prvostupnica (baccalaureus/baccalaurea) inženjer/inženjerka elektrotehnike (sveučilišni/a prvostupnik/ prvostupnica (baccalaureus/baccalaurea) inženjer/inženjerka elektrotehnike)
Type of resourceText
File originBorn digital
Access conditionsOpen access
Terms of useLicence In copyright icon
Created on2019-10-28 12:05:49