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undergraduate thesis
Izvedba sučelja FRISC-V procesora prema mreži na čipu
Zagreb: University of Zagreb, Faculty of Electrical Engineering and Computing, 2022. urn:nbn:hr:168:915975
Hanžek, Luka
University of Zagreb
Faculty of Electrical Engineering and Computing

Institutional repository: FER Repository

Cite this document

Hanžek, L. (2022). Izvedba sučelja FRISC-V procesora prema mreži na čipu (Undergraduate thesis). Zagreb: University of Zagreb, Faculty of Electrical Engineering and Computing. Retrieved from https://urn.nsk.hr/urn:nbn:hr:168:915975

Hanžek, Luka. "Izvedba sučelja FRISC-V procesora prema mreži na čipu." Undergraduate thesis, University of Zagreb, Faculty of Electrical Engineering and Computing, 2022. https://urn.nsk.hr/urn:nbn:hr:168:915975

Hanžek, Luka. "Izvedba sučelja FRISC-V procesora prema mreži na čipu." Undergraduate thesis, University of Zagreb, Faculty of Electrical Engineering and Computing, 2022. https://urn.nsk.hr/urn:nbn:hr:168:915975

Hanžek, L. (2022). 'Izvedba sučelja FRISC-V procesora prema mreži na čipu', Undergraduate thesis, University of Zagreb, Faculty of Electrical Engineering and Computing, accessed 26 December 2024, https://urn.nsk.hr/urn:nbn:hr:168:915975

Hanžek L. Izvedba sučelja FRISC-V procesora prema mreži na čipu [Undergraduate thesis]. Zagreb: University of Zagreb, Faculty of Electrical Engineering and Computing; 2022 [cited 2024 December 26] Available at: https://urn.nsk.hr/urn:nbn:hr:168:915975

L. Hanžek, "Izvedba sučelja FRISC-V procesora prema mreži na čipu", Undergraduate thesis, University of Zagreb, Faculty of Electrical Engineering and Computing, Zagreb, 2022. Available at: https://urn.nsk.hr/urn:nbn:hr:168:915975

Metadata
TitleIzvedba sučelja FRISC-V procesora prema mreži na čipu
Title (english)Implementation of FRISC-V network on chip interface
AuthorLuka Hanžek
MentorMario Kovač (mentor)
Committee memberMario Kovač (član povjerenstva)
Committee memberJosip Knezović (član povjerenstva)
Committee memberDaniel Hofman (član povjerenstva)
GranterUniversity of Zagreb
Faculty of Electrical Engineering and Computing
Zagreb
Defense date and country2022-07-01, Croatia
Scientific / art field,
discipline and subdiscipline		TECHNICAL SCIENCES
Computing
Abstract
U ovom radu predstavljena je i ispitana izvedba sučelja prema memoriji za RISC-V jezgru koje omogućava istovremeno povezivanje procesora s vanjskim sklopovljem i povezivanje memorije s podatkovnom i instrukcijskom sabirnicom procesora. Dana je ideja nadogradnje trenutnog rješenja za spajanje prema mreži na čipu. Opisan je postupak izrade rješenja. Rješenje je izvedeno i testirano pomoću Xilinx alata i Verilog\System Verilog jezika za opis sklopovlja.
Abstract (english)
This thesis presents an implementaion and testing of RISC-V memory interface which enables simultaneous linkeage of memory with external hardware and linkeage of memory with processors instruction and data busses. An idea of further extending the solution to support connecting to system on a chip is presented. The solution is built and tested using Xilinx tools and Verilog\System Verilog hardware decsription language.
Keywords
Keywords (english)
Languagecroatian
URN:NBNurn:nbn:hr:168:915975
Study programmeTitle: Computing
Study programme type: university
Study level: undergraduate
Academic / professional title: sveučilišni/a prvostupnik/ prvostupnica (baccalaureus/baccalaurea) inženjer/inženjerka računarstva (sveučilišni/a prvostupnik/ prvostupnica (baccalaureus/baccalaurea) inženjer/inženjerka računarstva)
Type of resourceText
File originBorn digital
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Created on2023-01-15 10:16:58