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undergraduate thesis
Dizajn gradivnih komponenti procesora arhitekture RISC-V za programabilnu logiku
Zagreb: University of Zagreb, Faculty of Electrical Engineering and Computing, 2022. urn:nbn:hr:168:104076
Šarić, Stjepan
University of Zagreb
Faculty of Electrical Engineering and Computing

Institutional repository: FER Repository

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Šarić, S. (2022). Dizajn gradivnih komponenti procesora arhitekture RISC-V za programabilnu logiku (Undergraduate thesis). Zagreb: University of Zagreb, Faculty of Electrical Engineering and Computing. Retrieved from https://urn.nsk.hr/urn:nbn:hr:168:104076

Šarić, Stjepan. "Dizajn gradivnih komponenti procesora arhitekture RISC-V za programabilnu logiku." Undergraduate thesis, University of Zagreb, Faculty of Electrical Engineering and Computing, 2022. https://urn.nsk.hr/urn:nbn:hr:168:104076

Šarić, Stjepan. "Dizajn gradivnih komponenti procesora arhitekture RISC-V za programabilnu logiku." Undergraduate thesis, University of Zagreb, Faculty of Electrical Engineering and Computing, 2022. https://urn.nsk.hr/urn:nbn:hr:168:104076

Šarić, S. (2022). 'Dizajn gradivnih komponenti procesora arhitekture RISC-V za programabilnu logiku', Undergraduate thesis, University of Zagreb, Faculty of Electrical Engineering and Computing, accessed 28 December 2024, https://urn.nsk.hr/urn:nbn:hr:168:104076

Šarić S. Dizajn gradivnih komponenti procesora arhitekture RISC-V za programabilnu logiku [Undergraduate thesis]. Zagreb: University of Zagreb, Faculty of Electrical Engineering and Computing; 2022 [cited 2024 December 28] Available at: https://urn.nsk.hr/urn:nbn:hr:168:104076

S. Šarić, "Dizajn gradivnih komponenti procesora arhitekture RISC-V za programabilnu logiku", Undergraduate thesis, University of Zagreb, Faculty of Electrical Engineering and Computing, Zagreb, 2022. Available at: https://urn.nsk.hr/urn:nbn:hr:168:104076

Metadata
TitleDizajn gradivnih komponenti procesora arhitekture RISC-V za programabilnu logiku
Title (english)Design of RISC-V ISA Processor Components for Programmable Logic Implementation
AuthorStjepan Šarić
MentorJosip Knezović (mentor)
Committee memberJosip Knezović (član povjerenstva)
Committee memberDanko Basch (član povjerenstva)
Committee memberIgor Čavrak (član povjerenstva)
GranterUniversity of Zagreb
Faculty of Electrical Engineering and Computing
Zagreb
Defense date and country2022-09-07, Croatia
Scientific / art field,
discipline and subdiscipline		TECHNICAL SCIENCES
Computing
Abstract
RISC-V arhitektura je skupa instrukcija otvorenog strandarda koja postaje sve popularnija pri dizajniranju raznih sklopova. Fakultet elektrotehnike i računarstva u Zagrebu nastoji napraviti funkcionalni simulator za RISC-V. Ovaj rad opisuje skup RISC-V instrukcija i RISC-V simulator te daje primjere kako simulator radi i komunicira sa komponentama kao što su vanjske jedinice te temperaturni sklop.
Abstract (english)
RISC-V is open standard instruction set architecture which is becoming more popular for designing various hardware components. Faculty of electrical engineering and computing in Zagreb is developing simulator for RISC-V. This paper describes set of RISC-V instructions, RISC-V simulator and gives examples of working simulator and his communication with components such as input and output units and temperature device.
Keywords
Keywords (english)
Languagecroatian
URN:NBNurn:nbn:hr:168:104076
Study programmeTitle: Computing
Study programme type: university
Study level: undergraduate
Academic / professional title: sveučilišni/a prvostupnik/ prvostupnica (baccalaureus/baccalaurea) inženjer/inženjerka računarstva (sveučilišni/a prvostupnik/ prvostupnica (baccalaureus/baccalaurea) inženjer/inženjerka računarstva)
Type of resourceText
File originBorn digital
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Created on2023-01-15 11:17:39