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master's thesis
Projektiranje sklopova protočnog analogno-digitalnog pretvornika u 180 nm CMOS tehnologiji
Zagreb: University of Zagreb, Faculty of Electrical Engineering and Computing, 2024. urn:nbn:hr:168:192038
Vrdoljak, Jakov
University of Zagreb
Faculty of Electrical Engineering and Computing

Institutional repository: FER Repository

Cite this document

Vrdoljak, J. (2024). Projektiranje sklopova protočnog analogno-digitalnog pretvornika u 180 nm CMOS tehnologiji (Master's thesis). Zagreb: University of Zagreb, Faculty of Electrical Engineering and Computing. Retrieved from https://urn.nsk.hr/urn:nbn:hr:168:192038

Vrdoljak, Jakov. "Projektiranje sklopova protočnog analogno-digitalnog pretvornika u 180 nm CMOS tehnologiji." Master's thesis, University of Zagreb, Faculty of Electrical Engineering and Computing, 2024. https://urn.nsk.hr/urn:nbn:hr:168:192038

Vrdoljak, Jakov. "Projektiranje sklopova protočnog analogno-digitalnog pretvornika u 180 nm CMOS tehnologiji." Master's thesis, University of Zagreb, Faculty of Electrical Engineering and Computing, 2024. https://urn.nsk.hr/urn:nbn:hr:168:192038

Vrdoljak, J. (2024). 'Projektiranje sklopova protočnog analogno-digitalnog pretvornika u 180 nm CMOS tehnologiji', Master's thesis, University of Zagreb, Faculty of Electrical Engineering and Computing, accessed 03 April 2025, https://urn.nsk.hr/urn:nbn:hr:168:192038

Vrdoljak J. Projektiranje sklopova protočnog analogno-digitalnog pretvornika u 180 nm CMOS tehnologiji [Master's thesis]. Zagreb: University of Zagreb, Faculty of Electrical Engineering and Computing; 2024 [cited 2025 April 03] Available at: https://urn.nsk.hr/urn:nbn:hr:168:192038

J. Vrdoljak, "Projektiranje sklopova protočnog analogno-digitalnog pretvornika u 180 nm CMOS tehnologiji", Master's thesis, University of Zagreb, Faculty of Electrical Engineering and Computing, Zagreb, 2024. Available at: https://urn.nsk.hr/urn:nbn:hr:168:192038

Metadata
TitleProjektiranje sklopova protočnog analogno-digitalnog pretvornika u 180 nm CMOS tehnologiji
Title (english)Circuit design for pipeline analog-digital converter in 180 nm CMOS technology
AuthorJakov Vrdoljak
MentorTvrtko Mandić (mentor)
Committee memberTvrtko Mandić (predsjednik povjerenstva)
Committee memberVladimir Čeperić (član povjerenstva)
Committee memberMarko Koričić (član povjerenstva)
GranterUniversity of Zagreb
Faculty of Electrical Engineering and Computing
Zagreb
Defense date and country2024-07-15, Croatia
Abstract
Projektirana je analogna sklopka s konstantnim prenaponom i uspoređene su njezine karakteristike s konvencionalnom analognom sklopkom, uzimajući u obzir maksimalni hod ulaznog napona, izobličenja i omjer signala i šuma. Projektirano je pojačalo s preklopljenom kaskodom, generatorom napajanja i referentne struje te pokretačkim sklopom. Za ovaj sklop provedene su istosmjerna i izmjenična analiza te analiza stabilnosti. Izrađen je topološki nacrt, ekstrahirane su parazitne komponente, a... More simulacije su ponovljene s parazitnim komponentama i uspoređene s rezultatima bez njih. Projektirano je pojačalo s preklapajućim kapacitetima koje se koristi u protočnom A/D pretvorniku, prilagođeno brzinu pretvorbe od 1 MS/s. Izrađen je topološki nacrt projektiranih blokova te su ekstrahirani parazitni elementi. Provedena je karakterizacija blokova s ekstrahiranim parazitnim elementima s obzirom na varijacije tehnološkog procesa, napona napajanja i temperature. Less
Abstract (english)
A bootstrap switch with constant overvoltage was designed, and its characteristics were compared with a conventional analog switch, taking into account the maximum range of input voltage, distortion, and signal-to-noise ratio. An amplifier with a folded cascode, power supply generator, reference current generator, and startup circuit was designed. For this circuit, DC and AC analysis, as well as stability analysis, were conducted. A topological layout was created, parasitic... More components were extracted, and simulations were repeated with parasitic components and compared to the results without them. An amplifier with switched capacitors, used in a pipelined A/D converter, was designed, adapted for a conversion speed of 1 MS/s. A topological layout of the designed blocks was created, and parasitic elements were extracted. Characterization of the blocks with the extracted parasitic elements was conducted, considering variations in the technological process, supply voltage, and temperature. Less
Keywords
Keywords (english)
Languagecroatian
URN:NBNurn:nbn:hr:168:192038
Study programmeTitle: Electrical Engineering and Information Technology
Study programme type: university
Study level: graduate
Academic / professional title: magistar/magistra inženjer/inženjerka elektrotehnike i informacijske tehnologije (magistar/magistra inženjer/inženjerka elektrotehnike i informacijske tehnologije)
Type of resourceText
File originBorn digital
Access conditionsOpen access
Terms of useLicence In copyright icon
Public note
Created on2024-10-12 22:27:24
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