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master's thesis
Implementacija CPRI sučelja na FPGA sklopovlju
Zagreb: University of Zagreb, Faculty of Electrical Engineering and Computing, 2017. urn:nbn:hr:168:316915
Ričković, Krešimir
University of Zagreb
Faculty of Electrical Engineering and Computing

Institutional repository: FER Repository

Cite this document

Ričković, K. (2017). Implementacija CPRI sučelja na FPGA sklopovlju (Master's thesis). Zagreb: University of Zagreb, Faculty of Electrical Engineering and Computing. Retrieved from https://urn.nsk.hr/urn:nbn:hr:168:316915

Ričković, Krešimir. "Implementacija CPRI sučelja na FPGA sklopovlju." Master's thesis, University of Zagreb, Faculty of Electrical Engineering and Computing, 2017. https://urn.nsk.hr/urn:nbn:hr:168:316915

Ričković, Krešimir. "Implementacija CPRI sučelja na FPGA sklopovlju." Master's thesis, University of Zagreb, Faculty of Electrical Engineering and Computing, 2017. https://urn.nsk.hr/urn:nbn:hr:168:316915

Ričković, K. (2017). 'Implementacija CPRI sučelja na FPGA sklopovlju', Master's thesis, University of Zagreb, Faculty of Electrical Engineering and Computing, accessed 15 June 2024, https://urn.nsk.hr/urn:nbn:hr:168:316915

Ričković K. Implementacija CPRI sučelja na FPGA sklopovlju [Master's thesis]. Zagreb: University of Zagreb, Faculty of Electrical Engineering and Computing; 2017 [cited 2024 June 15] Available at: https://urn.nsk.hr/urn:nbn:hr:168:316915

K. Ričković, "Implementacija CPRI sučelja na FPGA sklopovlju", Master's thesis, University of Zagreb, Faculty of Electrical Engineering and Computing, Zagreb, 2017. Available at: https://urn.nsk.hr/urn:nbn:hr:168:316915

Metadata
TitleImplementacija CPRI sučelja na FPGA sklopovlju
Title (english)FPGA Implementation of CPRI Interface
AuthorKrešimir Ričković
MentorMladen Vučić (mentor)
Committee memberMladen Vučić (predsjednik povjerenstva)
Committee memberDavor Petrinović (član povjerenstva)
Committee memberGoran Molnar (član povjerenstva)
GranterUniversity of Zagreb
Faculty of Electrical Engineering and Computing
Zagreb
Defense date and country2017-07-05, Croatia
Scientific / art field,
discipline and subdiscipline		TECHNICAL SCIENCES
Computing
Scientific / art field,
discipline and subdiscipline		TECHNICAL SCIENCES
Electrical Engineering
Abstract
U ovom radu su opisani dijelovi CPRI specifikacije prvog sloja relevantni za izvedbu programskog rješenja. Objašnjen je princip serijalizacije i deserijalizacije podataka putem SerDes bloka. Objašnjen je princip dobivanja sinkroniziranog signala takta s optimalnim faznim pomakom putem CDR bloka. Opisane su mogućnosti i ograničenja razvojne pločice koja je služila za testiranje razvijenog programskog rješenja. Opisano je razvijeno programsko rješenje u programskom jeziku C i opisan je način korištenja razvijenih aplikacija. Opisano je razvijeno programsko rješenje u programskom jeziku VHDL s pripadajućim vremenskim dijagramima pojedinih razvijenih komponenti.
Abstract (english)
Parts of layer 1 CPRI specification relevant for implementing software solution are described in this thesis. Data serialization and deserialization principle using SerDes block is explained. Extracting synchronized clock signal with optimal phase shift using CDR block is also explained. Features and restrictions of development board Zedboard, which was used for testing developed software solution, are listed and explained. Developed software solution in programming language C and usage of developed software solution is also explained. Developed software solution in programming language VHDL with accompanying time diagrams of developed components is also explained in this thesis.
Keywords
Keywords (english)
Languagecroatian
URN:NBNurn:nbn:hr:168:316915
Study programmeTitle: Electrical Engineering and Information Technology
Study programme type: university
Study level: graduate
Academic / professional title: magistar/magistra inženjer/inženjerka elektrotehnike i informacijske tehnologije (magistar/magistra inženjer/inženjerka elektrotehnike i informacijske tehnologije)
Type of resourceText
File originBorn digital
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Created on2019-03-14 00:27:43