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master's thesis
Dizajn i FPGA implementacija izoštrenih CIC filtara sa zadanim brojem zbrajala
Zagreb: University of Zagreb, Faculty of Electrical Engineering and Computing, 2018. urn:nbn:hr:168:934426
Šalković, Mislav
University of Zagreb
Faculty of Electrical Engineering and Computing

Institutional repository: FER Repository

Cite this document

Šalković, M. (2018). Dizajn i FPGA implementacija izoštrenih CIC filtara sa zadanim brojem zbrajala (Master's thesis). Zagreb: University of Zagreb, Faculty of Electrical Engineering and Computing. Retrieved from https://urn.nsk.hr/urn:nbn:hr:168:934426

Šalković, Mislav. "Dizajn i FPGA implementacija izoštrenih CIC filtara sa zadanim brojem zbrajala." Master's thesis, University of Zagreb, Faculty of Electrical Engineering and Computing, 2018. https://urn.nsk.hr/urn:nbn:hr:168:934426

Šalković, Mislav. "Dizajn i FPGA implementacija izoštrenih CIC filtara sa zadanim brojem zbrajala." Master's thesis, University of Zagreb, Faculty of Electrical Engineering and Computing, 2018. https://urn.nsk.hr/urn:nbn:hr:168:934426

Šalković, M. (2018). 'Dizajn i FPGA implementacija izoštrenih CIC filtara sa zadanim brojem zbrajala', Master's thesis, University of Zagreb, Faculty of Electrical Engineering and Computing, accessed 29 August 2024, https://urn.nsk.hr/urn:nbn:hr:168:934426

Šalković M. Dizajn i FPGA implementacija izoštrenih CIC filtara sa zadanim brojem zbrajala [Master's thesis]. Zagreb: University of Zagreb, Faculty of Electrical Engineering and Computing; 2018 [cited 2024 August 29] Available at: https://urn.nsk.hr/urn:nbn:hr:168:934426

M. Šalković, "Dizajn i FPGA implementacija izoštrenih CIC filtara sa zadanim brojem zbrajala", Master's thesis, University of Zagreb, Faculty of Electrical Engineering and Computing, Zagreb, 2018. Available at: https://urn.nsk.hr/urn:nbn:hr:168:934426

Metadata
TitleDizajn i FPGA implementacija izoštrenih CIC filtara sa zadanim brojem zbrajala
Title (english)Design and FPGA Implementation of Sharpened CIC Filters With Specified Number of Adders
AuthorMislav Šalković
MentorMladen Vučić (mentor)
Committee memberMladen Vučić (predsjednik povjerenstva)
Committee memberDavor Petrinović (član povjerenstva)
Committee memberGoran Molnar (član povjerenstva)
GranterUniversity of Zagreb
Faculty of Electrical Engineering and Computing
Zagreb
Defense date and country2018-09-28, Croatia
Scientific / art field,
discipline and subdiscipline		TECHNICAL SCIENCES
Electrical Engineering
Abstract
U ovom diplomskom radu bavili smo se postupcima dizajna i realizacije polinomno izoštrenih CIC filtara. U razvojnom okruženju MATLAB napravljeni su izračuni polinomijalnih koeficijenata zapisanih kao potencije broja dva korištenjem minimax dizajna za CIC filtar u pojasu preklapanja spektara. S izračunatim koeficijentima razvili smo RTL model izoštrenog CIC filtra koristeći jezik za opis sklopovlja VHDL. Model je optimiziran za implementaciju na programabilnim logičkim poljima (FPGA) te je za isti napravljeno ispitno okruženje, provedena je simulacija te je model uhodan na stvarnom sklopovlju.
Abstract (english)
In this master’s thesis we have been learning about design a realisation of polynomial sharpened CIC filters. In MATLAB desktop environment, a tool has been designed in the purpose of calculating polynomial coefficients in the form of powers of two by using the minimax method for the CIC folding bands. With the calculated polynomials we have developed a physically achievable model of the CIC filter using the program language VHDL. The model is optimised for implementation on FPGA systems. Finally, a testbench has been made for the model and with all simulations run and checked, the model has been transferred to a real development board.
Keywords
Keywords (english)
Languagecroatian
URN:NBNurn:nbn:hr:168:934426
Study programmeTitle: Electrical Engineering and Information Technology
Study programme type: university
Study level: graduate
Academic / professional title: magistar/magistra inženjer/inženjerka elektrotehnike i informacijske tehnologije (magistar/magistra inženjer/inženjerka elektrotehnike i informacijske tehnologije)
Type of resourceText
File originBorn digital
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Created on2019-03-14 01:04:56