With the development of the semiconductor technology, the VLSI circuits are becoming larger and are composed of ever smaller elements – transistors. Because of this, the interconnections are becoming more complex while the speed demands are higher. The modelling of the interconnect is gaining importance and it is usually modelled using resistances, capacitances, and inductances. In this thesis, the influence and importance of each element is given. Starting from Maxwell's equations the defining relations for the extraction methods are derived. Because of the complexity of the capacitance and inductance extraction, a number of extraction methods and methods for increasing the speed of the extraction are presented. The inductance modelling problems are described. From the known values of the interconnect model elements, relations for the signal delay can be derived. The formulae for the Elmore delay and the transmission line delay for RC and RLC models are presented. Propagation delay and crosstalk for short, medium, and long wires are given. Based on the interconnect characteristics, some design rules are derived. The 8-bit data bus was simulated as an example on which the interconnect characteristics can be examined. The simulation results confirm the predictions presented in previous chapters. The characteristics of the materials used for interconnect manufacturing are given in appendix A and the technological processes are presented in appendix B.