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undergraduate thesis
Projektiranje sklopa za testiranje integriranih sklopova u 180 nm CMOS tehnologiji
Zagreb: University of Zagreb, Faculty of Electrical Engineering and Computing, 2019. urn:nbn:hr:168:615884
Bertolan, Roman
University of Zagreb
Faculty of Electrical Engineering and Computing

Institutional repository: FER Repository

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Bertolan, R. (2019). Projektiranje sklopa za testiranje integriranih sklopova u 180 nm CMOS tehnologiji (Undergraduate thesis). Zagreb: University of Zagreb, Faculty of Electrical Engineering and Computing. Retrieved from https://urn.nsk.hr/urn:nbn:hr:168:615884

Bertolan, Roman. "Projektiranje sklopa za testiranje integriranih sklopova u 180 nm CMOS tehnologiji." Undergraduate thesis, University of Zagreb, Faculty of Electrical Engineering and Computing, 2019. https://urn.nsk.hr/urn:nbn:hr:168:615884

Bertolan, Roman. "Projektiranje sklopa za testiranje integriranih sklopova u 180 nm CMOS tehnologiji." Undergraduate thesis, University of Zagreb, Faculty of Electrical Engineering and Computing, 2019. https://urn.nsk.hr/urn:nbn:hr:168:615884

Bertolan, R. (2019). 'Projektiranje sklopa za testiranje integriranih sklopova u 180 nm CMOS tehnologiji', Undergraduate thesis, University of Zagreb, Faculty of Electrical Engineering and Computing, accessed 29 December 2024, https://urn.nsk.hr/urn:nbn:hr:168:615884

Bertolan R. Projektiranje sklopa za testiranje integriranih sklopova u 180 nm CMOS tehnologiji [Undergraduate thesis]. Zagreb: University of Zagreb, Faculty of Electrical Engineering and Computing; 2019 [cited 2024 December 29] Available at: https://urn.nsk.hr/urn:nbn:hr:168:615884

R. Bertolan, "Projektiranje sklopa za testiranje integriranih sklopova u 180 nm CMOS tehnologiji", Undergraduate thesis, University of Zagreb, Faculty of Electrical Engineering and Computing, Zagreb, 2019. Available at: https://urn.nsk.hr/urn:nbn:hr:168:615884

Metadata
TitleProjektiranje sklopa za testiranje integriranih sklopova u 180 nm CMOS tehnologiji
Title (english)Design of test interface of integrated circuits in 180-nm CMOS technology
AuthorRoman Bertolan
MentorAdrijan Barić (mentor)
Committee memberAdrijan Barić (predsjednik povjerenstva)
Committee memberHrvoje Štimac (član povjerenstva)
Committee memberVlatko Galić (član povjerenstva)
GranterUniversity of Zagreb
Faculty of Electrical Engineering and Computing
Zagreb
Defense date and country2019-09-17, Croatia
Scientific / art field,
discipline and subdiscipline		TECHNICAL SCIENCES
Electrical Engineering
Abstract
Mikroelektronika i integrirani sklopovi predstavljaju okosnicu moderne civilizacije. Osnovna komponenta svakog mikroelektroničkog sklopa je tranzistor čije je otkriće dovelo do nevjerojatnog razvoja poluvodičkih tehnologija, od svog otkrića pa sve do danas. Oscilatori koji generiraju signal takta svrstavaju se među najvažnije gradivne blokove integriranih sklopova. Opisani postupak projektiranja zahtijeva duboko poznavanje teorije na razini tranzistora, od osnovnog poznavanja rada pojedinog tranzistora pa sve do toga kako grupe tranzistora zajedno tvore analogne i digitalne sklopove. Kombiniranjem analognih i digitalnih sklopova mogu se postići značajna ostvarenja u mikroelektroničkoj industriji. Kako bi se postigli željeni rezultati i dobio ispravan rad sklopa, bitno je znati da ništa nije idelano te se trebaju ispitati svi mogući realni slučajevi kako bi se na kraju dobio kvalitetan i stabilan proizvod koji će raditi u svim specificiranim uvjetima. U ovom radu opisan je postupak projektiranja ispitnog sklopa za generator takta od 1 Hz u 180 nanometarskoj CMOS tehnologiji. Opisani su podsklopovi koji tvore ispitni sklop. Pomoću sklopovskih simulacija u programskom sustavu Cadence pokazano je kako ispitni sklop ispravno radi u širokom opsegu ulaznih signala te za sve rubne tehnološke parametre.
Abstract (english)
Microelectronics and integrated circuits are the backbone of modern civilisation.The fundamental building block of any microelectronic circuit is the transistor, since its discovery to this very day. The oscillator is considered to be one of the most important circuit building blocks, since most modern devices require a clock signal. The design process of this project requires deep understanding of the transistor theory, as well as understanding how each circuit block interacts to form the whole integrated circuit. Combining analog and digital circuits can yield significant results in the microelectronics industry. To achieve the desired results and produce a functioning chip, it is of utmost importance that we disconnect from the ideal view of the schematic and accept the non-ideal real world model. This in turn will allow us to be sure that our circuit will function for a wide range of operating conditions. This paper describes the process of designing and implementing a 1 Hz clock generator test interface in180 nm CMOS technology. Every module of the test interface is described independently. With the aid of the Cadence simulation tools, it is shown that the test interface functions properly for a wide variety of operating conditions, input parameters and corner cases.
Keywords
Keywords (english)
Languageenglish
URN:NBNurn:nbn:hr:168:615884
Study programmeTitle: Electrical Engineering and Information Technology
Study programme type: university
Study level: undergraduate
Academic / professional title: sveučilišni/a prvostupnik/ prvostupnica (baccalaureus/baccalaurea) inženjer/inženjerka elektrotehnike i informacijske tehnologije (sveučilišni/a prvostupnik/ prvostupnica (baccalaureus/baccalaurea) inženjer/inženjerka elektrotehnike i informacijske tehnologije)
Type of resourceText
File originBorn digital
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Created on2020-01-07 16:45:19