The theme of this research paper is an integer frequency divider which is used in a frequency synthesizer for wireless comunnication at 2.4 GHz according to IEEE 802.11 standard. The divider is designed using a 180 nm CMOS technology from the TSMC company. The synthesizer is made as a Phase-Locking Loop which has to generate a signal from the local oscillator depending on the selected channel and the divider is located in the feedback of the loop. The integer divider has to divide a GHz signal and the result has to be a MHz signal which is compared to the signal from the local oscillator. With the use of digital logic it is possible to program the integer divider to have the divide ratio from 2400 to 2527 which includes all the channels within the standard. The divider is consisted of 3 parts: Dual-Modulus Prescaler, Swallow Counter and Program Counter. The Dual-Modulus Prescaler is the only part that is operating at GHz frequencies which is why Current-Mode Logic is used to design it. Current-Mode Logic uses differential gates and has logic voltage levels that are equal to 1.8 V (high) and 1.3 V (low). For the final design, the divide ratio od Dual-Modulus Prescaler is 15/16. Swallow Counter and Program Counter are constructed as 7 and 8-bit UP counters using the standard CMOS logic gates with logic voltage leves of 1.8 V and 0 V. The UP counter is designed with T flip-flops with asynchronous inputs. The divide ratio of the Swallow Counter can be programed which means that the output frequency of the divider can be programed too.