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master's thesis
Izvedba sklopovskog akceleratora za procesor RISC-V
Zagreb: University of Zagreb, Faculty of Electrical Engineering and Computing, 2019. urn:nbn:hr:168:359499
Macan, Luka
University of Zagreb
Faculty of Electrical Engineering and Computing

Institutional repository: FER Repository

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Macan, L. (2019). Izvedba sklopovskog akceleratora za procesor RISC-V (Master's thesis). Zagreb: University of Zagreb, Faculty of Electrical Engineering and Computing. Retrieved from https://urn.nsk.hr/urn:nbn:hr:168:359499

Macan, Luka. "Izvedba sklopovskog akceleratora za procesor RISC-V." Master's thesis, University of Zagreb, Faculty of Electrical Engineering and Computing, 2019. https://urn.nsk.hr/urn:nbn:hr:168:359499

Macan, Luka. "Izvedba sklopovskog akceleratora za procesor RISC-V." Master's thesis, University of Zagreb, Faculty of Electrical Engineering and Computing, 2019. https://urn.nsk.hr/urn:nbn:hr:168:359499

Macan, L. (2019). 'Izvedba sklopovskog akceleratora za procesor RISC-V', Master's thesis, University of Zagreb, Faculty of Electrical Engineering and Computing, accessed 13 January 2025, https://urn.nsk.hr/urn:nbn:hr:168:359499

Macan L. Izvedba sklopovskog akceleratora za procesor RISC-V [Master's thesis]. Zagreb: University of Zagreb, Faculty of Electrical Engineering and Computing; 2019 [cited 2025 January 13] Available at: https://urn.nsk.hr/urn:nbn:hr:168:359499

L. Macan, "Izvedba sklopovskog akceleratora za procesor RISC-V", Master's thesis, University of Zagreb, Faculty of Electrical Engineering and Computing, Zagreb, 2019. Available at: https://urn.nsk.hr/urn:nbn:hr:168:359499

Metadata
TitleIzvedba sklopovskog akceleratora za procesor RISC-V
Title (english)Implementation of hardware accelerator for RISC-V processor
AuthorLuka Macan
MentorMario Kovač (mentor)
Committee memberMario Kovač (predsjednik povjerenstva)
Committee memberJosip Knezović (član povjerenstva)
Committee memberDaniel Hofman (član povjerenstva)
GranterUniversity of Zagreb
Faculty of Electrical Engineering and Computing
Zagreb
Defense date and country2019-07-04, Croatia
Scientific / art field,
discipline and subdiscipline		TECHNICAL SCIENCES
Computing
Abstract
Tema ovog diplomskog rada je implementacija akceleratora za obradu slike za RISC-V procesor unutar heterogenog sustava. HERO platforma je odabrana za istraživanje i razvoj, s obzirom na to da već implementira heterogeni sustav na čipu (engl. Heterogeneous System on Chip (HESoC)) i posjeduje programsku podršku za njegovo programiranje. Za sklopovsko ubrzanje izabran je algoritam pretvorbe piksela iz RGB u Y'CbCr prostor boja. Navedeni algoritam implementiran je kao sklopovski procesni ubrzivač (engl. Hardware Processing Engine (HWPE)). Za integraciju s HERO platformom, iskorišteni su gotovi HWPE moduli. Implementacija postiže ubrzanje od 24 puta u odnosu na programsku implementaciju na jednoj RISC-V jezgri te 3 puta u odnosu na paralelnu implementaciju za 8 RISC-V jezgri.
Abstract (english)
The topic of this theses was the implementation of an image processing accelerator for a RISC-V processing core in a heterogeneous system. The HERO platform, which implements a heterogeneous system on chip and its software stack, was used for research and development of the accelerator. The accelerated algorithm was the color conversion from RGB to Y'CbCr space. It was implemented as a hardware processing engine. Ready HWPE modules were used for integration with the HERO platform. The implementation achieved a speedup of 24 times compared to the single core RISC-V software implementation and a speedup of 3 times compared to the 8 core RISC-V parallel implementation.
Keywords
Keywords (english)
Languageenglish
URN:NBNurn:nbn:hr:168:359499
Study programmeTitle: Computing
Study programme type: university
Study level: graduate
Academic / professional title: magistar/magistra inženjer/inženjerka računarstva (magistar/magistra inženjer/inženjerka računarstva)
Type of resourceText
File originBorn digital
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Created on2020-01-07 19:55:33