prikaz prve stranice dokumenta Implementacija TensorFlow modela na FPGA platformi
No public access
master's thesis
Implementacija TensorFlow modela na FPGA platformi
Zagreb: University of Zagreb, Faculty of Electrical Engineering and Computing, 2019. urn:nbn:hr:168:100844
Martinčević, Jurica
University of Zagreb
Faculty of Electrical Engineering and Computing

Institutional repository: FER Repository

Cite this document

Martinčević, J. (2019). Implementacija TensorFlow modela na FPGA platformi (Master's thesis). Zagreb: University of Zagreb, Faculty of Electrical Engineering and Computing. Retrieved from https://urn.nsk.hr/urn:nbn:hr:168:100844

Martinčević, Jurica. "Implementacija TensorFlow modela na FPGA platformi." Master's thesis, University of Zagreb, Faculty of Electrical Engineering and Computing, 2019. https://urn.nsk.hr/urn:nbn:hr:168:100844

Martinčević, Jurica. "Implementacija TensorFlow modela na FPGA platformi." Master's thesis, University of Zagreb, Faculty of Electrical Engineering and Computing, 2019. https://urn.nsk.hr/urn:nbn:hr:168:100844

Martinčević, J. (2019). 'Implementacija TensorFlow modela na FPGA platformi', Master's thesis, University of Zagreb, Faculty of Electrical Engineering and Computing, accessed 26 November 2024, https://urn.nsk.hr/urn:nbn:hr:168:100844

Martinčević J. Implementacija TensorFlow modela na FPGA platformi [Master's thesis]. Zagreb: University of Zagreb, Faculty of Electrical Engineering and Computing; 2019 [cited 2024 November 26] Available at: https://urn.nsk.hr/urn:nbn:hr:168:100844

J. Martinčević, "Implementacija TensorFlow modela na FPGA platformi", Master's thesis, University of Zagreb, Faculty of Electrical Engineering and Computing, Zagreb, 2019. Available at: https://urn.nsk.hr/urn:nbn:hr:168:100844

Metadata
TitleImplementacija TensorFlow modela na FPGA platformi
Title (english)Implementation of TensorFlow Models on FPGA Platform
AuthorJurica Martinčević
MentorHrvoje Džapo (mentor)
Committee memberHrvoje Džapo (predsjednik povjerenstva)
Committee memberDavor Petrinović (član povjerenstva)
Committee memberDarko Vasić (član povjerenstva)
GranterUniversity of Zagreb
Faculty of Electrical Engineering and Computing
Zagreb
Defense date and country2019-07-12, Croatia
Scientific / art field,
discipline and subdiscipline		TECHNICAL SCIENCES
Computing
Abstract
Konvolucijske neuronske mreže pokazale su se kao izvrstan odabir u području obrade slike, a sve se više primjenjuju i u raznim drugim područjima. Najčešće se neuronske se mreže izvode na računalnim sustavima veće procesorske snage, kao što su poslužitelji i osobna računala dok se rijeđe izvode na ugradbenim računalnim sustavima. U radu je istražena mogućnost izvođenja konvolucijskih neuronskih mreža na ugradbenim računalnim sustavima koji sadrže FPGA sklopove, a za takve sustave moguće je generirati sklopovske akceleratore za konvolucijske neuronske mreže.U sklopu rada razvijene su u jeziku VHDL neke od jedinica koje izvode operacije konvolucijske mreže. Također su provedena mjerenja vremena izvođenja 2D konvolucije na osobnom računalu te su dobiveni rezultati uspoređeni s rezultatima dobivenim simulacijom jedinice za 2D konvoluciju na FPGA. U radu je pokazano kako je moguće prenijeti neuronsku mrežu iz TensorFlow modela na FPGA platformu te je istraženo koji se problemi mogu pojaviti prilikom prijenosa. Pokazano je kako je najveći problem manjak memorije na samom FPGA sklopu, ali taj problem je umanjen dizajnom komponenti koje ne zahtijevaju veliku količinu memorije.
Abstract (english)
Convolutional neural networks are nowadays among the best choices for solving various problems in the image processing domain, as well as many other different application fields. Neural networks are usually executed on computer systems with high processing power, such as servers and personal computers, and they are rarely run on embedded systems. This thesis explores the posibilities of running convolutional neural networks on embedded systems that contain FPGA circuits, since it is possible to generate hardware accelerators for convolutional neural networks. Work on this thesis encompassed the development of some hardware units for convolutional neural network operations in VHDL language. Moreover, the performance of generated FPGA hardware accelerator for convolutional neural networks was compared with performance of personal computer by means of simulations and runtime measurements. This work also shows how to transfer neural network from TensorFlow model to FPGA platform, along with analysis of possible problems in this process. One of the main shortcomings is the lack of memory resources on FPGA hardware, what was addressed by designing the components with low memory requirements.
Keywords
Keywords (english)
Languagecroatian
URN:NBNurn:nbn:hr:168:100844
Study programmeTitle: Computing
Study programme type: university
Study level: graduate
Academic / professional title: magistar/magistra inženjer/inženjerka računarstva (magistar/magistra inženjer/inženjerka računarstva)
Type of resourceText
File originBorn digital
Access conditionsClosed access
Terms of useLicence In copyright icon
Public note
Created on2020-01-07 20:07:57