prikaz prve stranice dokumenta Izvedba sklopovskog vektorskog akceleratora za brojeve s pomičnim zarezom za procesor RISC-V
No public access
master's thesis
Izvedba sklopovskog vektorskog akceleratora za brojeve s pomičnim zarezom za procesor RISC-V
Zagreb: University of Zagreb, Faculty of Electrical Engineering and Computing, 2019. urn:nbn:hr:168:387407
Milković, Tomislav
University of Zagreb
Faculty of Electrical Engineering and Computing

Institutional repository: FER Repository

Cite this document

Milković, T. (2019). Izvedba sklopovskog vektorskog akceleratora za brojeve s pomičnim zarezom za procesor RISC-V (Master's thesis). Zagreb: University of Zagreb, Faculty of Electrical Engineering and Computing. Retrieved from https://urn.nsk.hr/urn:nbn:hr:168:387407

Milković, Tomislav. "Izvedba sklopovskog vektorskog akceleratora za brojeve s pomičnim zarezom za procesor RISC-V." Master's thesis, University of Zagreb, Faculty of Electrical Engineering and Computing, 2019. https://urn.nsk.hr/urn:nbn:hr:168:387407

Milković, Tomislav. "Izvedba sklopovskog vektorskog akceleratora za brojeve s pomičnim zarezom za procesor RISC-V." Master's thesis, University of Zagreb, Faculty of Electrical Engineering and Computing, 2019. https://urn.nsk.hr/urn:nbn:hr:168:387407

Milković, T. (2019). 'Izvedba sklopovskog vektorskog akceleratora za brojeve s pomičnim zarezom za procesor RISC-V', Master's thesis, University of Zagreb, Faculty of Electrical Engineering and Computing, accessed 26 December 2024, https://urn.nsk.hr/urn:nbn:hr:168:387407

Milković T. Izvedba sklopovskog vektorskog akceleratora za brojeve s pomičnim zarezom za procesor RISC-V [Master's thesis]. Zagreb: University of Zagreb, Faculty of Electrical Engineering and Computing; 2019 [cited 2024 December 26] Available at: https://urn.nsk.hr/urn:nbn:hr:168:387407

T. Milković, "Izvedba sklopovskog vektorskog akceleratora za brojeve s pomičnim zarezom za procesor RISC-V", Master's thesis, University of Zagreb, Faculty of Electrical Engineering and Computing, Zagreb, 2019. Available at: https://urn.nsk.hr/urn:nbn:hr:168:387407

Metadata
TitleIzvedba sklopovskog vektorskog akceleratora za brojeve s pomičnim zarezom za procesor RISC-V
Title (english)Implementation of hardware vector floating point accelerator for RISC-V processor
AuthorTomislav Milković
MentorMario Kovač (mentor)
Committee memberMario Kovač (predsjednik povjerenstva)
Committee memberJosip Knezović (član povjerenstva)
Committee memberDaniel Hofman (član povjerenstva)
GranterUniversity of Zagreb
Faculty of Electrical Engineering and Computing
Zagreb
Defense date and country2019-07-04, Croatia
Scientific / art field,
discipline and subdiscipline		TECHNICAL SCIENCES
Computing
Abstract
Tema ovog diplomskog rada je izrada sklopovskog vektorskog akceleratora za obradu brojeva s pomičnim zarezom prema IEEE-754 standardu te njegova primjena u sustavu s RISC-V procesorom. Za sustav u koji će akcelerator biti integriran odabrana je HERO heterogena razvojna platforma zbog svoje prilagodljivosti i otvorenosti. U radu su istražena i opisana sučelja sklopovskih obradbenih jedinica (HWPE) za HERO platformu te sklopovlje i programska podrška HERO platforme. Opisana je sklopovska arhitektura i programski model akceleratora te je provedena usporedba ubrzanja u odnosu na obradu brojeva s pomičnim zarezom na RISC-V jezgrama prisutnim na HERO platformi.
Abstract (english)
The topic of this thesis is implementation of hardware vector floating point accelerator according to IEEE-754 standard and its usage in a system with RISC-V processor. HERO - a heterogeneous research platform was chosen as the system in which the accelerator will be integrated because of its flexibility and openness. Hardware processing engine (HWPE) interfaces are researched and described in this thesis, as well as HERO platform hardware and software stack. The hardware architecture and programming model of the accelerator is described and a speedup comparison is made between executing the floating point operations on the accelerator as opposed to executing them on the RISC-V cores present in the HERO platform.
Keywords
Keywords (english)
Languagecroatian
URN:NBNurn:nbn:hr:168:387407
Study programmeTitle: Computing
Study programme type: university
Study level: graduate
Academic / professional title: magistar/magistra inženjer/inženjerka računarstva (magistar/magistra inženjer/inženjerka računarstva)
Type of resourceText
File originBorn digital
Access conditionsClosed access
Terms of useLicence In copyright icon
Public note
Created on2020-01-07 20:31:14