This thesis presents the development of the wide-channel FinFET, which is based on the formation of the tall, high aspect-ratio, silicon fins. The introductory chapter gives a short overview of the development of CMOS devices, scaling concept and rules, and the challenges faced today by the CMOS industry. The major challenge for the future generations of CMOS circuits is the suppression of the short-channel effects in which Silicon-On-Insulator and double-gate MOSFETs offer significant improvement over the bulk devices. The double- or triple-gate FinFET is a series candidate for the replacement of bulk MOSFETs in some critical applications, such as low-power digital and high-gain analog circuits, due to its superior gate-coupling to the channel. Additionally, FinFET fabrication process has many similarities with the standard bulk process. The advantages of the tall silicon fins, i.e. wide channels per single fin, are laid out in the second chapter. The performance of the FinFETs strongly depends on their parasitic resistances and capacitances, and devices with the smaller number of fins promise improved frequency performance. Moreover, the current density per silicon area used is increased for taller silicon fins. The processing of the tall fins and wide-channel FinFET is divided into process modules which are analyzed and the possible solutions investigated with the goal of processing fins of 1 um height at a minimum, and 20 nm width or lower, on bulk silicon wafers. To meet the required dimensions, the silicon-nitride-spacer hard-mask was developed for the fin-etching with either an oxide sacrificial island etched by reactive-ion-etching, or silicon mesa etched by TMAH, used for the spacer formation. The etching of silicon fins requires extreme anisotropy and the best results are obtained by the crystallographic etching of (110) wafers in TMAH which exposes vertical (111) crystal planes. The fins are isolated from the silicon substrate by the deposition of thick silicon dioxide layer by LPCVD, oxide planarization using CMP and oxide etch-back in buffered-HF solution. The MOS gate-stack consisting of the thermal oxide and n+-polysilicon gate was used for both n- and p-type devices. In order to improve process reliability, the more conservative stack was developed with the target oxide-thickness of 5 nm. The investigation of the possible choices for polysilicon-gate etching showed that reactive-ion-etching recipes cannot meet the required etching selectivity to underlying gate-oxide and therefore, TMAH etching was used for the patterning of the gate. With lateral underetching taken into account, the shortest gates achieved in the process are estimated at 200 nm. A simple implantation and annealing scheme was utilized for the formation of the source and drain regions, and the contacts were placed on large pad areas. The TEM analysis revealed that the actual fin width is 2 nm, due to loss of silicon-fin width during oxidation and oxide removal steps. However, this offers the chance on investigating carrier transport on (111) surfaces with nanoscale dimensions of the channel. The electrical characterization show excellent subthreshold performance of both pFETs and nFETs. Drive current of the p-channel devices is in the range expected for the (111) surface orientation, but n-channel FET drive currents suffer from the gate depletion. The connections of the active part of the device with the source and drain contacts through the narrow fins causes significant series resistance which degrades some of device parameters. However, with the advanced gate etching process and the formation of gate spacers, the series resistances can be reduced to acceptable level by selective growth on fin sidewalls. The concept of wide-channel FinFET was successfully demonstrated with maximum reported fin heights and a significant margin for future improvement.