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master's thesis
Izvedba akceleratora za obradu slika za processor RISC-V
Zagreb: University of Zagreb, Faculty of Electrical Engineering and Computing, 2020. urn:nbn:hr:168:387175
Jakovac, Stjepan
University of Zagreb
Faculty of Electrical Engineering and Computing

Institutional repository: FER Repository

Cite this document

Jakovac, S. (2020). Izvedba akceleratora za obradu slika za processor RISC-V (Master's thesis). Zagreb: University of Zagreb, Faculty of Electrical Engineering and Computing. Retrieved from https://urn.nsk.hr/urn:nbn:hr:168:387175

Jakovac, Stjepan. "Izvedba akceleratora za obradu slika za processor RISC-V." Master's thesis, University of Zagreb, Faculty of Electrical Engineering and Computing, 2020. https://urn.nsk.hr/urn:nbn:hr:168:387175

Jakovac, Stjepan. "Izvedba akceleratora za obradu slika za processor RISC-V." Master's thesis, University of Zagreb, Faculty of Electrical Engineering and Computing, 2020. https://urn.nsk.hr/urn:nbn:hr:168:387175

Jakovac, S. (2020). 'Izvedba akceleratora za obradu slika za processor RISC-V', Master's thesis, University of Zagreb, Faculty of Electrical Engineering and Computing, accessed 28 December 2024, https://urn.nsk.hr/urn:nbn:hr:168:387175

Jakovac S. Izvedba akceleratora za obradu slika za processor RISC-V [Master's thesis]. Zagreb: University of Zagreb, Faculty of Electrical Engineering and Computing; 2020 [cited 2024 December 28] Available at: https://urn.nsk.hr/urn:nbn:hr:168:387175

S. Jakovac, "Izvedba akceleratora za obradu slika za processor RISC-V", Master's thesis, University of Zagreb, Faculty of Electrical Engineering and Computing, Zagreb, 2020. Available at: https://urn.nsk.hr/urn:nbn:hr:168:387175

Metadata
TitleIzvedba akceleratora za obradu slika za processor RISC-V
Title (english)Image processing accelerator for RISC-V processor
AuthorStjepan Jakovac
MentorMario Kovač (mentor)
Committee memberMario Kovač (predsjednik povjerenstva)
Committee memberHrvoje Mlinarić (član povjerenstva)
Committee memberJosip Knezović (član povjerenstva)
GranterUniversity of Zagreb
Faculty of Electrical Engineering and Computing
Zagreb
Defense date and country2020-07-13, Croatia
Scientific / art field,
discipline and subdiscipline		TECHNICAL SCIENCES
Computing
Abstract
Zadatak ovog rada je izvesti akcelerator za obradu slike za procesor RISC-V. Dan je kratak pregled razvoja i trenutno stanje dostupnih RISC-V jezgara. Za implementaciju akceleratora odabrana je HERO platforma razvijena suradnjom Sveučilišta ETH Zurich i Sveučilišta u Bologna-i. Algoritam koji će se ubrzati je DCT algoritam za transformaciju u frekvencijsko područje kod JPEG kompresije. Opisani su glavni protokoli i moduli potrebni za implementaciju i integraciju akceleratora. Odabran je specifični algoritam te je opisana njegova izvedba na nekoliko načina. Identificirane su prednosti i mane svakog od tih pristupa.
Abstract (english)
The goal of this paper is to implement image processing accelerator for RISC-V processor. A brief overview of development and currently available RISC-V cores is given. The HERO platform developed in cooperation between the ETH Zurich and the University of Bologna was selected for hosting the accelerator. An algorithm that will be accelerated is DCT algorithm for freqency transformation as defined by JPEG standard. Main protocols and modules required for accelerator implementation and integration are described. A specific algorithm was selected and few ways of implementing were presented. The advantages and disadvantages of each of these approaches have been identified.
Keywords
Keywords (english)
Languagecroatian
URN:NBNurn:nbn:hr:168:387175
Study programmeTitle: Computing
Study programme type: university
Study level: graduate
Academic / professional title: magistar/magistra inženjer/inženjerka računarstva (magistar/magistra inženjer/inženjerka računarstva)
Type of resourceText
File originBorn digital
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Created on2023-01-13 12:29:10