prikaz prve stranice dokumenta Implementacija 32-bitne RISC-V instrukcijske arhitekture otvorenog koda u FPGA sklopovlju
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master's thesis
Implementacija 32-bitne RISC-V instrukcijske arhitekture otvorenog koda u FPGA sklopovlju
Zagreb: University of Zagreb, Faculty of Electrical Engineering and Computing, 2021. urn:nbn:hr:168:561059
Žuglić, Ivan
University of Zagreb
Faculty of Electrical Engineering and Computing

Institutional repository: FER Repository

Cite this document

Žuglić, I. (2021). Implementacija 32-bitne RISC-V instrukcijske arhitekture otvorenog koda u FPGA sklopovlju (Master's thesis). Zagreb: University of Zagreb, Faculty of Electrical Engineering and Computing. Retrieved from https://urn.nsk.hr/urn:nbn:hr:168:561059

Žuglić, Ivan. "Implementacija 32-bitne RISC-V instrukcijske arhitekture otvorenog koda u FPGA sklopovlju." Master's thesis, University of Zagreb, Faculty of Electrical Engineering and Computing, 2021. https://urn.nsk.hr/urn:nbn:hr:168:561059

Žuglić, Ivan. "Implementacija 32-bitne RISC-V instrukcijske arhitekture otvorenog koda u FPGA sklopovlju." Master's thesis, University of Zagreb, Faculty of Electrical Engineering and Computing, 2021. https://urn.nsk.hr/urn:nbn:hr:168:561059

Žuglić, I. (2021). 'Implementacija 32-bitne RISC-V instrukcijske arhitekture otvorenog koda u FPGA sklopovlju', Master's thesis, University of Zagreb, Faculty of Electrical Engineering and Computing, accessed 23 November 2024, https://urn.nsk.hr/urn:nbn:hr:168:561059

Žuglić I. Implementacija 32-bitne RISC-V instrukcijske arhitekture otvorenog koda u FPGA sklopovlju [Master's thesis]. Zagreb: University of Zagreb, Faculty of Electrical Engineering and Computing; 2021 [cited 2024 November 23] Available at: https://urn.nsk.hr/urn:nbn:hr:168:561059

I. Žuglić, "Implementacija 32-bitne RISC-V instrukcijske arhitekture otvorenog koda u FPGA sklopovlju", Master's thesis, University of Zagreb, Faculty of Electrical Engineering and Computing, Zagreb, 2021. Available at: https://urn.nsk.hr/urn:nbn:hr:168:561059

Metadata
TitleImplementacija 32-bitne RISC-V instrukcijske arhitekture otvorenog koda u FPGA sklopovlju
Title (english)Implement a 32-bit RISC-V open-source instruction architecture in an FPGA hardware
AuthorIvan Žuglić
MentorDaniel Hofman (mentor)
Committee memberDaniel Hofman (predsjednik povjerenstva)
Committee memberDanko Basch (član povjerenstva)
Committee memberJosip Knezović (član povjerenstva)
GranterUniversity of Zagreb
Faculty of Electrical Engineering and Computing
Zagreb
Defense date and country2021-06-29, Croatia
Scientific / art field,
discipline and subdiscipline		TECHNICAL SCIENCES
Computing
Abstract
U ovome radu je prikazana i objašnjena cjelokupna implementacija RISC-V arhitekture osnovnog skupa instrukcija (RV32I). Dano je objašnjenje formata implementiranih instrukcija i pojedinih komponenti arhitekture koje su potrebne za njihovo ispravno izvođenje, te je naveden cjelokupni programski kod implementacije opisane arhitekture, kao i kodovi ispitnih programa kojima se provjerava ispravnost izvođenja pojedinih instrukcija u simulaciji i na ZedBoard FPGA sklopovlju. Također je napravljena analiza performansi i predložen je daljnji razvoj arhitekture.
Abstract (english)
This thesis describes and explains the entire implementation of RISC-V base instruction set architecture (RV32I). An explanation on the format of the implemented instructions is given, along with the explanation of each individual component of the architecture which is needed for their proper execution. In addition, the entire programming code of the architecture is given and explained as well as programming code of the test programs which check validity of the executed instructions in both the simulation and the ZedBoard FPGA. Performance analysis is also given, along with the proposal of the future development.
Keywords
Keywords (english)
Languagecroatian
URN:NBNurn:nbn:hr:168:561059
Study programmeTitle: Computing
Study programme type: university
Study level: graduate
Academic / professional title: magistar/magistra inženjer/inženjerka računarstva (magistar/magistra inženjer/inženjerka računarstva)
Type of resourceText
File originBorn digital
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Created on2023-01-13 16:33:03