prikaz prve stranice dokumenta Projektiranje sustava s fazno sinkroniziranom petljom u 180 nm CMOS tehnologiji
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undergraduate thesis
Projektiranje sustava s fazno sinkroniziranom petljom u 180 nm CMOS tehnologiji
Zagreb: University of Zagreb, Faculty of Electrical Engineering and Computing, 2020. urn:nbn:hr:168:003992
Žamboki, Andro
University of Zagreb
Faculty of Electrical Engineering and Computing

Institutional repository: FER Repository

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Žamboki, A. (2020). Projektiranje sustava s fazno sinkroniziranom petljom u 180 nm CMOS tehnologiji (Undergraduate thesis). Zagreb: University of Zagreb, Faculty of Electrical Engineering and Computing. Retrieved from https://urn.nsk.hr/urn:nbn:hr:168:003992

Žamboki, Andro. "Projektiranje sustava s fazno sinkroniziranom petljom u 180 nm CMOS tehnologiji." Undergraduate thesis, University of Zagreb, Faculty of Electrical Engineering and Computing, 2020. https://urn.nsk.hr/urn:nbn:hr:168:003992

Žamboki, Andro. "Projektiranje sustava s fazno sinkroniziranom petljom u 180 nm CMOS tehnologiji." Undergraduate thesis, University of Zagreb, Faculty of Electrical Engineering and Computing, 2020. https://urn.nsk.hr/urn:nbn:hr:168:003992

Žamboki, A. (2020). 'Projektiranje sustava s fazno sinkroniziranom petljom u 180 nm CMOS tehnologiji', Undergraduate thesis, University of Zagreb, Faculty of Electrical Engineering and Computing, accessed 26 November 2024, https://urn.nsk.hr/urn:nbn:hr:168:003992

Žamboki A. Projektiranje sustava s fazno sinkroniziranom petljom u 180 nm CMOS tehnologiji [Undergraduate thesis]. Zagreb: University of Zagreb, Faculty of Electrical Engineering and Computing; 2020 [cited 2024 November 26] Available at: https://urn.nsk.hr/urn:nbn:hr:168:003992

A. Žamboki, "Projektiranje sustava s fazno sinkroniziranom petljom u 180 nm CMOS tehnologiji", Undergraduate thesis, University of Zagreb, Faculty of Electrical Engineering and Computing, Zagreb, 2020. Available at: https://urn.nsk.hr/urn:nbn:hr:168:003992

Metadata
TitleProjektiranje sustava s fazno sinkroniziranom petljom u 180 nm CMOS tehnologiji
Title (english)Design of phase-locked loop in 180-nm CMOS technology
AuthorAndro Žamboki
MentorAdrijan Barić (mentor)
Committee memberAdrijan Barić (predsjednik povjerenstva)
Committee memberMarko Koričić (član povjerenstva)
Committee memberJosip Bačmaga (član povjerenstva)
GranterUniversity of Zagreb
Faculty of Electrical Engineering and Computing
Zagreb
Defense date and country2020-07-07, Croatia
Scientific / art field,
discipline and subdiscipline		TECHNICAL SCIENCES
Electrical Engineering
Abstract
Oblikovanje dijelova fazno spregnute petlje zvani "Kontrola radnog umjera" (DCC) i "Pretvorba nivoa napona" (LS) u CMOS 180 nm integriranoj tehnologiji. Sustav mora moći pretvoriti ulazni signal takta iz niže naponske domene u višu te osigurati da signal takta na izlazu ima radni omjer točno 50%. Sustav mora raditi u svim najgorim rubnim slučajevima. Također se moraju provesti simulacije cijele fazno spregnute petlje i demonstrirati njena mogućnost slijeđenja frekvencije ulaznog signala te otpornost na izlazne smetnje.
Abstract (english)
Design of the parts of a phase locked loop (PLL) called "Duty cycle control" and "Level shifter" in CMOS 180 nm integrated technology. The system has to have the ability to shift the input clock signal from a lower voltage domain to a higher and ensure that the duty cycle of the output clock signal is exactly 50%. The system has to work in all possible worst case corners. Top level simulations of the whole PLL have to be performed and they need to demonstrate the PLL's ability to follow the input frequency and resist outside disturbances.
Keywords
Keywords (english)
Languageenglish
URN:NBNurn:nbn:hr:168:003992
Study programmeTitle: Electrical Engineering and Information Technology
Study programme type: university
Study level: undergraduate
Academic / professional title: sveučilišni/a prvostupnik/ prvostupnica (baccalaureus/baccalaurea) inženjer/inženjerka elektrotehnike i informacijske tehnologije (sveučilišni/a prvostupnik/ prvostupnica (baccalaureus/baccalaurea) inženjer/inženjerka elektrotehnike i informacijske tehnologije)
Type of resourceText
File originBorn digital
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Created on2023-01-14 10:21:26