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undergraduate thesis
Simulacija obrade videa na VexRiscv implementaciji procesora RISC-V
Zagreb: University of Zagreb, Faculty of Electrical Engineering and Computing, 2021. urn:nbn:hr:168:505786
Holik, Matija
University of Zagreb
Faculty of Electrical Engineering and Computing

Institutional repository: FER Repository

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Holik, M. (2021). Simulacija obrade videa na VexRiscv implementaciji procesora RISC-V (Undergraduate thesis). Zagreb: University of Zagreb, Faculty of Electrical Engineering and Computing. Retrieved from https://urn.nsk.hr/urn:nbn:hr:168:505786

Holik, Matija. "Simulacija obrade videa na VexRiscv implementaciji procesora RISC-V." Undergraduate thesis, University of Zagreb, Faculty of Electrical Engineering and Computing, 2021. https://urn.nsk.hr/urn:nbn:hr:168:505786

Holik, Matija. "Simulacija obrade videa na VexRiscv implementaciji procesora RISC-V." Undergraduate thesis, University of Zagreb, Faculty of Electrical Engineering and Computing, 2021. https://urn.nsk.hr/urn:nbn:hr:168:505786

Holik, M. (2021). 'Simulacija obrade videa na VexRiscv implementaciji procesora RISC-V', Undergraduate thesis, University of Zagreb, Faculty of Electrical Engineering and Computing, accessed 27 December 2024, https://urn.nsk.hr/urn:nbn:hr:168:505786

Holik M. Simulacija obrade videa na VexRiscv implementaciji procesora RISC-V [Undergraduate thesis]. Zagreb: University of Zagreb, Faculty of Electrical Engineering and Computing; 2021 [cited 2024 December 27] Available at: https://urn.nsk.hr/urn:nbn:hr:168:505786

M. Holik, "Simulacija obrade videa na VexRiscv implementaciji procesora RISC-V", Undergraduate thesis, University of Zagreb, Faculty of Electrical Engineering and Computing, Zagreb, 2021. Available at: https://urn.nsk.hr/urn:nbn:hr:168:505786

Metadata
TitleSimulacija obrade videa na VexRiscv implementaciji procesora RISC-V
Title (english)Simulation of Video Processing on a VexRiscv Implementation of a RISC-V Processor
AuthorMatija Holik
MentorDaniel Hofman (mentor)
Committee memberDaniel Hofman (predsjednik povjerenstva)
Committee memberAlen Duspara (član povjerenstva)
Committee memberLuka Macan (član povjerenstva)
GranterUniversity of Zagreb
Faculty of Electrical Engineering and Computing
Zagreb
Defense date and country2021-07-01, Croatia
Scientific / art field,
discipline and subdiscipline		TECHNICAL SCIENCES
Computing
Abstract
Rastom popularnosti RISC-V arhitekture, na tržištu se pojavio niz otvorenih mikroarhitektura koje ju implementiraju. Njihova pristupačnost daje im osjetnu prednost na komercijalnim alternativama te se postavlja pitanje kolika je praktična upotrebljivost tih otvorenih rješenja? Ovaj rad u kratko opisuje principe iza RISC-V arhitekture te se fokusira na VexRiscv implementaciju iste. Uz performanse i strukturu samog VexRiscv-a obrađeni su i ugradbeni računalni sustavi Murax SoC i Saxon SoC temeljeni na VexRiscv jezgri te je za oba izgrađena prilagođena Linux distribucija korištenjem Buildroot alata. Također su spomenute neke alternativne konfiguracije primjerenije za specifične zadaće. Rad formiranog sustava verificiran je u simulatoru te sklopovski, sintezom na ULX3S FPGA sklopu. Konačno, testirana je primjenjivost sustava u domeni obrade videa pomoću programa FFmpeg gdje je kao glavna metrika korišteno prosječno vrijeme obrade uzoraka. Jedno-jezgreni, ugradbeni sustav čini nestandardnu konfiguraciju u procesno zahtjevnoj domeni poput video obrade pa su dobiveni rezultati više akademske nego pragmatične prirode te su za saznanja veće praktične korisnosti potrebna daljnja istraživanja.
Abstract (english)
With the growth in popularity of the RISC-V ISA, many open-source implementations based on it have appeared on the market. Their openness gives them a clear advantage over the proprietary counterparts, which leaves the question of just how practically applicable are these open solutions? This thesis goes over the principles behind the RISC-V ISA and focuses specifically on its VexRiscv implementation. Besides VexRiscv’s performance and implementation details, two embedded systems by the names of Murax SoC and Saxon SoC, based on the VexRiscv core, and the accompanying Linux distributions, custom-made using the Buildroot utility, are also discussed. Additionally, the thesis goes over some alternative system designs geared towards specific applications. The system’s functionality was verified using both simulation and hardware, namely an ULX3S FPGA board. Finally, the video processing capabilities were assessed using the FFmpeg software package, using the average sample processing time as the primary metric. It is not common to see a single-core, embedded computer system used for CPU intensive tasks, such as video processing, and so the acquired results are more academic than pragmatic in nature. Consequently, to obtain more practically useful information, further research is needed.
Keywords
Keywords (english)
Languagecroatian
URN:NBNurn:nbn:hr:168:505786
Study programmeTitle: Computing
Study programme type: university
Study level: undergraduate
Academic / professional title: sveučilišni/a prvostupnik/ prvostupnica (baccalaureus/baccalaurea) inženjer/inženjerka računarstva (sveučilišni/a prvostupnik/ prvostupnica (baccalaureus/baccalaurea) inženjer/inženjerka računarstva)
Type of resourceText
File originBorn digital
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Created on2023-01-14 20:34:39