prikaz prve stranice dokumenta Arhitektura RISC procesora
Access restricted to students and staff of home institution
undergraduate thesis
Arhitektura RISC procesora
Varaždin: University of Zagreb, Faculty of Organization and Informatics Varaždin, 2014. urn:nbn:hr:211:196624
Rupčić, Leo
University of Zagreb
Faculty of Organization and Informatics
Department of Computing and Technology

Institutional repository: Faculty of Organization and Informatics - Digital Repository

Cite this document

Rupčić, L. (2014). Arhitektura RISC procesora (Undergraduate thesis). Varaždin: University of Zagreb, Faculty of Organization and Informatics. Retrieved from https://urn.nsk.hr/urn:nbn:hr:211:196624

Rupčić, Leo. "Arhitektura RISC procesora." Undergraduate thesis, University of Zagreb, Faculty of Organization and Informatics, 2014. https://urn.nsk.hr/urn:nbn:hr:211:196624

Rupčić, Leo. "Arhitektura RISC procesora." Undergraduate thesis, University of Zagreb, Faculty of Organization and Informatics, 2014. https://urn.nsk.hr/urn:nbn:hr:211:196624

Rupčić, L. (2014). 'Arhitektura RISC procesora', Undergraduate thesis, University of Zagreb, Faculty of Organization and Informatics, accessed 04 August 2024, https://urn.nsk.hr/urn:nbn:hr:211:196624

Rupčić L. Arhitektura RISC procesora [Undergraduate thesis]. Varaždin: University of Zagreb, Faculty of Organization and Informatics; 2014 [cited 2024 August 04] Available at: https://urn.nsk.hr/urn:nbn:hr:211:196624

L. Rupčić, "Arhitektura RISC procesora", Undergraduate thesis, University of Zagreb, Faculty of Organization and Informatics, Varaždin, 2014. Available at: https://urn.nsk.hr/urn:nbn:hr:211:196624

Metadata
TitleArhitektura RISC procesora
Title (english)RISC processor architecture
AuthorLeo Rupčić
MentorIvan Magdalenić (mentor)
MBZ: 244501
Committee memberNikola Ivković
MBZ: 306480
GranterUniversity of Zagreb
Faculty of Organization and Informatics
(Department of Computing and Technology)
Varaždin
Defense date and country2014-09-19, Croatia
Scientific / art field,
discipline and subdiscipline		SOCIAL SCIENCES
Information and Communication Sciences
Organization and Informatics
Abstract
Rad obuhvaća arhitekturu RISC procesora, primjer RISC procesora, usporedba RISC i CISC arhitektura, ARM procesor, hazardi u protočnoj strukturi.
Keywords
Languagecroatian
URN:NBNurn:nbn:hr:211:196624
Study programmeTitle: Information Systems
Study programme type: university
Study level: undergraduate
Academic / professional title: sveučilišni/a prvostupnik/prvostupnica (baccalaureus/baccalaurea) informatike (sveučilišni/a prvostupnik/prvostupnica (baccalaureus/baccalaurea) informatike)
Type of resourceText
File originBorn digital
Access conditionsAccess restricted to students and staff of home institution
Terms of useLicence Attribution-NonCommercial-NoDerivs 3.0 Unported (CC BY-NC-ND 3.0) icon
Public noteZbog automatske konverzije u pdf moguće su manje nepodudarnosti između originalnog dokumenta i verzije pohranjene u repozitorij.
Created on2017-01-26 09:15:05