prikaz prve stranice dokumenta Implementacija FIR filtra zasnovanog na FPGA za digitalnu obradu zvuka u realnom vremenu
  Download
PDF 2.7 MB
master's thesis
Implementacija FIR filtra zasnovanog na FPGA za digitalnu obradu zvuka u realnom vremenu
Osijek: Josip Juraj Strossmayer University of Osijek, Faculty of Electrical Engineering, Computer Science and Information Technology Osijek, 2018. urn:nbn:hr:200:208108
Krajcar, Krunoslav
Josip Juraj Strossmayer University of Osijek
Faculty of Electrical Engineering, Computer Science and Information Technology Osijek
Department of Communications
Chair of Electronics and Microelectronics

Institutional repository: Faculty of Electrical Engineering, Computer Science and Information Technology Osijek

Cite this document

Krajcar, K. (2018). Implementacija FIR filtra zasnovanog na FPGA za digitalnu obradu zvuka u realnom vremenu (Master's thesis). Osijek: Josip Juraj Strossmayer University of Osijek, Faculty of Electrical Engineering, Computer Science and Information Technology Osijek. Retrieved from https://urn.nsk.hr/urn:nbn:hr:200:208108

Krajcar, Krunoslav. "Implementacija FIR filtra zasnovanog na FPGA za digitalnu obradu zvuka u realnom vremenu." Master's thesis, Josip Juraj Strossmayer University of Osijek, Faculty of Electrical Engineering, Computer Science and Information Technology Osijek, 2018. https://urn.nsk.hr/urn:nbn:hr:200:208108

Krajcar, Krunoslav. "Implementacija FIR filtra zasnovanog na FPGA za digitalnu obradu zvuka u realnom vremenu." Master's thesis, Josip Juraj Strossmayer University of Osijek, Faculty of Electrical Engineering, Computer Science and Information Technology Osijek, 2018. https://urn.nsk.hr/urn:nbn:hr:200:208108

Krajcar, K. (2018). 'Implementacija FIR filtra zasnovanog na FPGA za digitalnu obradu zvuka u realnom vremenu', Master's thesis, Josip Juraj Strossmayer University of Osijek, Faculty of Electrical Engineering, Computer Science and Information Technology Osijek, accessed 20 May 2024, https://urn.nsk.hr/urn:nbn:hr:200:208108

Krajcar K. Implementacija FIR filtra zasnovanog na FPGA za digitalnu obradu zvuka u realnom vremenu [Master's thesis]. Osijek: Josip Juraj Strossmayer University of Osijek, Faculty of Electrical Engineering, Computer Science and Information Technology Osijek; 2018 [cited 2024 May 20] Available at: https://urn.nsk.hr/urn:nbn:hr:200:208108

K. Krajcar, "Implementacija FIR filtra zasnovanog na FPGA za digitalnu obradu zvuka u realnom vremenu", Master's thesis, Josip Juraj Strossmayer University of Osijek, Faculty of Electrical Engineering, Computer Science and Information Technology Osijek, Osijek, 2018. Available at: https://urn.nsk.hr/urn:nbn:hr:200:208108

Metadata
TitleImplementacija FIR filtra zasnovanog na FPGA za digitalnu obradu zvuka u realnom vremenu
Title (english)FPGA implementation of FIR filter used for digital audio processing
AuthorKrunoslav Krajcar
MentorMarijan Herceg (mentor)
Committee memberMarijan Herceg (predsjednik povjerenstva)
Committee memberMario Vranješ (član povjerenstva)
Committee memberRatko Grbić (član povjerenstva)
GranterJosip Juraj Strossmayer University of Osijek
Faculty of Electrical Engineering, Computer Science and Information Technology Osijek
(Department of Communications)
(Chair of Electronics and Microelectronics)
Osijek
Defense date and country2018-09-20, Croatia
Scientific / art field,
discipline and subdiscipline		TECHNICAL SCIENCES
Electrical Engineering
Electronics
Abstract
U radu opisan je postupak dizajniranja FIR digitalnog filtra, te njegova implementacija u FPGA. Pojašnjene su korištenih tehnologija te opisan rad svakog entiteta dizajna. Provedene su simulacije filtra u MatLabu te usporedba s mjerenim rezultatima implementiranog filtra. Dizajn je izveden u Vivado razvojnom okruženju na Zynq-7000 SoC-u, gdje se konfiguracija parametra filtra vrši uz pomoć procesora. Rad je proširen na ekvilizator s deset FIR filtara koji rade paralelno.
Abstract (english)
The paper explains the process of designing an FIR filter and his implementation in the FPGA. The used technologies and entities for the design are further explained. Simulations of the filter's behavior are made in MatLab and compared to the measured frequency response of the implemented filter. Vivado Design Suite is used to create the design on the Zynq-7000 SoC, where the configuration of the filter is done with the processor. The paper is expanded to the Equilizer that has 10 FIR filters working parallelly.
Keywords
Keywords (english)
Languagecroatian
URN:NBNurn:nbn:hr:200:208108
Study programmeTitle: Graduate University Study Programme in Electrical Engineering; specializations in: Communications and Informatics, Power Engineering
Course: Communications and Informatics
Study programme type: university
Study level: graduate
Academic / professional title: magistar/magistra inženjer/inženjerka elektrotehnike (magistar/magistra inženjer/inženjerka elektrotehnike)
Type of resourceText
File originBorn digital
Access conditionsOpen access
Terms of useLicence In copyright icon
Created on2018-10-04 15:04:59