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master's thesis
Implementacija JPEG kodera zasnovanog na FPGA
Osijek: Josip Juraj Strossmayer University of Osijek, Faculty of Electrical Engineering, Computer Science and Information Technology Osijek, 2018. urn:nbn:hr:200:334016
Valek, Igor
Josip Juraj Strossmayer University of Osijek
Faculty of Electrical Engineering, Computer Science and Information Technology Osijek
Department of Communications
Chair of Multimedia Systems and Digital Television

Institutional repository: Faculty of Electrical Engineering, Computer Science and Information Technology Osijek

Cite this document

Valek, I. (2018). Implementacija JPEG kodera zasnovanog na FPGA (Master's thesis). Osijek: Josip Juraj Strossmayer University of Osijek, Faculty of Electrical Engineering, Computer Science and Information Technology Osijek. Retrieved from https://urn.nsk.hr/urn:nbn:hr:200:334016

Valek, Igor. "Implementacija JPEG kodera zasnovanog na FPGA." Master's thesis, Josip Juraj Strossmayer University of Osijek, Faculty of Electrical Engineering, Computer Science and Information Technology Osijek, 2018. https://urn.nsk.hr/urn:nbn:hr:200:334016

Valek, Igor. "Implementacija JPEG kodera zasnovanog na FPGA." Master's thesis, Josip Juraj Strossmayer University of Osijek, Faculty of Electrical Engineering, Computer Science and Information Technology Osijek, 2018. https://urn.nsk.hr/urn:nbn:hr:200:334016

Valek, I. (2018). 'Implementacija JPEG kodera zasnovanog na FPGA', Master's thesis, Josip Juraj Strossmayer University of Osijek, Faculty of Electrical Engineering, Computer Science and Information Technology Osijek, accessed 30 November 2024, https://urn.nsk.hr/urn:nbn:hr:200:334016

Valek I. Implementacija JPEG kodera zasnovanog na FPGA [Master's thesis]. Osijek: Josip Juraj Strossmayer University of Osijek, Faculty of Electrical Engineering, Computer Science and Information Technology Osijek; 2018 [cited 2024 November 30] Available at: https://urn.nsk.hr/urn:nbn:hr:200:334016

I. Valek, "Implementacija JPEG kodera zasnovanog na FPGA", Master's thesis, Josip Juraj Strossmayer University of Osijek, Faculty of Electrical Engineering, Computer Science and Information Technology Osijek, Osijek, 2018. Available at: https://urn.nsk.hr/urn:nbn:hr:200:334016

Metadata
TitleImplementacija JPEG kodera zasnovanog na FPGA
Title (english)FPGA implementation of JPEG coder
AuthorIgor Valek
MentorMario Vranješ (mentor)
MentorLeon Šneler (mentor)
Committee memberMario Vranješ (predsjednik povjerenstva)
Committee memberMarijan Herceg (član povjerenstva)
Committee memberLeon Šneler (član povjerenstva)
GranterJosip Juraj Strossmayer University of Osijek
Faculty of Electrical Engineering, Computer Science and Information Technology Osijek
(Department of Communications)
(Chair of Multimedia Systems and Digital Television)
Osijek
Defense date and country2018-12-21, Croatia
Scientific / art field,
discipline and subdiscipline		TECHNICAL SCIENCES
Electrical Engineering
Telecommunications and Informatics
Abstract
U radu je opisana izrada i implementacija JPEG kodera zasnovanog na FPGA tehnologiji. Objašnjene su sve tehnologije potrebne za rad sustava, te postupak dizajniranja i funkcionalnosti svakog pojedinog modula. Nad sustavom su izvršena mjerenja, u kojima su se mjerila brzina obrade slike, te postignuti omjer kompresije za različite faktore kvalitete slike. Sustav se dizajnirao u Vivado razvojnom okruženju na Zynq-7000 SoC-u, gdje je procesor unosio konfiguracijske parametre a hardverski sustav vršio obradu slike. Rad sustava testiran je na više različitih slika, gdje se pokazalo da sustav ispunjava sve zadatke propisane JPEG normom
Abstract (english)
The paper describes the development and implementation of the JPEG coder based on the FPGA. All the technologies needed to operate the system, as well as the design and functionality of each module are explained. Measurements were performed over the system, measuring the speed of the image processing, and the compression ratio achieved for different image quality factors. The system was designed in the Vivado development environment on the Zynq-7000 SoC, where the processor introduced configuration parameters, and the hardware system processed the image. The system operation was tested on several different images, where it was shown that the system fulfilled all the tasks prescribed by the JPEG standard.
Keywords
Keywords (english)
Languagecroatian
URN:NBNurn:nbn:hr:200:334016
Study programmeTitle: Graduate University Study Programme in Electrical Engineering; specializations in: Communications and Informatics, Power Engineering
Course: Communications and Informatics
Study programme type: university
Study level: graduate
Academic / professional title: magistar/magistra inženjer/inženjerka elektrotehnike (magistar/magistra inženjer/inženjerka elektrotehnike)
Type of resourceText
File originBorn digital
Access conditionsOpen access
Terms of useLicence In copyright icon
Created on2018-12-21 14:48:24