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undergraduate thesis
Izvedba protočne strukture FRISC-V procesora
Zagreb: University of Zagreb, Faculty of Electrical Engineering and Computing, 2022. urn:nbn:hr:168:133848
Grzunov, Matej
University of Zagreb
Faculty of Electrical Engineering and Computing

Institutional repository: FER Repository

Cite this document

Grzunov, M. (2022). Izvedba protočne strukture FRISC-V procesora (Undergraduate thesis). Zagreb: University of Zagreb, Faculty of Electrical Engineering and Computing. Retrieved from https://urn.nsk.hr/urn:nbn:hr:168:133848

Grzunov, Matej. "Izvedba protočne strukture FRISC-V procesora." Undergraduate thesis, University of Zagreb, Faculty of Electrical Engineering and Computing, 2022. https://urn.nsk.hr/urn:nbn:hr:168:133848

Grzunov, Matej. "Izvedba protočne strukture FRISC-V procesora." Undergraduate thesis, University of Zagreb, Faculty of Electrical Engineering and Computing, 2022. https://urn.nsk.hr/urn:nbn:hr:168:133848

Grzunov, M. (2022). 'Izvedba protočne strukture FRISC-V procesora', Undergraduate thesis, University of Zagreb, Faculty of Electrical Engineering and Computing, accessed 26 December 2024, https://urn.nsk.hr/urn:nbn:hr:168:133848

Grzunov M. Izvedba protočne strukture FRISC-V procesora [Undergraduate thesis]. Zagreb: University of Zagreb, Faculty of Electrical Engineering and Computing; 2022 [cited 2024 December 26] Available at: https://urn.nsk.hr/urn:nbn:hr:168:133848

M. Grzunov, "Izvedba protočne strukture FRISC-V procesora", Undergraduate thesis, University of Zagreb, Faculty of Electrical Engineering and Computing, Zagreb, 2022. Available at: https://urn.nsk.hr/urn:nbn:hr:168:133848

Metadata
TitleIzvedba protočne strukture FRISC-V procesora
Title (english)Implementation of FIRSC-V pipeline
AuthorMatej Grzunov
MentorMario Kovač (mentor)
Committee memberMario Kovač (član povjerenstva)
Committee memberJosip Knezović (član povjerenstva)
Committee memberDaniel Hofman (član povjerenstva)
GranterUniversity of Zagreb
Faculty of Electrical Engineering and Computing
Zagreb
Defense date and country2022-07-01, Croatia
Scientific / art field,
discipline and subdiscipline		TECHNICAL SCIENCES
Computing
Abstract
U sklopu ovog završnog rada dizajnirana je, izvedena i verificirana protočna struktura FRISC-V 32-bitne procesorske jezgre, koja može izvršavati naredbe RV32I podskupa naredbi RISC-V arhitekture skupa naredbi. Protočna struktura sastavljena je od 5 razina koje omogućavaju dohvaćanje podataka iz memorije, njihovu obradu, te pohranu nazad u memoriju. Proučene su vrste hazarda koje se mogu pojaviti, te njihovo razrješavanje kroz izvedbu harvardske arhitekture pristupa memoriji, upravljačke signale za izazivanje internog zastoja protočne strukture, i ubacivanje mjehurića u protočnu strukturu. Ispitivanje protočne strukture provedeno je na malim programskim odsječcima, provjerom postupne promjene stanja registara, podatkovne memorije i internih signala.
Abstract (english)
The core part of this thesis was the design, implementation, and verification of the FRISC-V processor core’s instruction pipeline, which supports the execution of instructions defined by the RV32I subset of the RISC-V instruction set architecture. The 5-stage instruction pipeline with in-order instruction execution supports reading data from the data memory, doing various calculations on it, and then writing it back into memory. The potential hazard situations were ascertained and resolved by designing the processor core with the Harvard memory access architecture in mind, creating specialized stall logic in the pipeline, and by injecting pipeline bubbles. The pipeline was tested by running small, assembled, bare machine programs, all the while inspecting the contents of registers, the data memory, and internal signal states.
Keywords
Keywords (english)
Languagecroatian
URN:NBNurn:nbn:hr:168:133848
Study programmeTitle: Computing
Study programme type: university
Study level: undergraduate
Academic / professional title: sveučilišni/a prvostupnik/ prvostupnica (baccalaureus/baccalaurea) inženjer/inženjerka računarstva (sveučilišni/a prvostupnik/ prvostupnica (baccalaureus/baccalaurea) inženjer/inženjerka računarstva)
Type of resourceText
File originBorn digital
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Created on2023-01-15 10:15:29