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master's thesis
Sustav za testiranje i verifikaciju brzih sučelja između dva uređaja AMD/Xilinx UltraScale+ FPGA
Zagreb: University of Zagreb, Faculty of Electrical Engineering and Computing, 2023. urn:nbn:hr:168:834529
Galić, Mirko
University of Zagreb
Faculty of Electrical Engineering and Computing

Institutional repository: FER Repository

Cite this document

Galić, M. (2023). Sustav za testiranje i verifikaciju brzih sučelja između dva uređaja AMD/Xilinx UltraScale+ FPGA (Master's thesis). Zagreb: University of Zagreb, Faculty of Electrical Engineering and Computing. Retrieved from https://urn.nsk.hr/urn:nbn:hr:168:834529

Galić, Mirko. "Sustav za testiranje i verifikaciju brzih sučelja između dva uređaja AMD/Xilinx UltraScale+ FPGA." Master's thesis, University of Zagreb, Faculty of Electrical Engineering and Computing, 2023. https://urn.nsk.hr/urn:nbn:hr:168:834529

Galić, Mirko. "Sustav za testiranje i verifikaciju brzih sučelja između dva uređaja AMD/Xilinx UltraScale+ FPGA." Master's thesis, University of Zagreb, Faculty of Electrical Engineering and Computing, 2023. https://urn.nsk.hr/urn:nbn:hr:168:834529

Galić, M. (2023). 'Sustav za testiranje i verifikaciju brzih sučelja između dva uređaja AMD/Xilinx UltraScale+ FPGA', Master's thesis, University of Zagreb, Faculty of Electrical Engineering and Computing, accessed 28 December 2024, https://urn.nsk.hr/urn:nbn:hr:168:834529

Galić M. Sustav za testiranje i verifikaciju brzih sučelja između dva uređaja AMD/Xilinx UltraScale+ FPGA [Master's thesis]. Zagreb: University of Zagreb, Faculty of Electrical Engineering and Computing; 2023 [cited 2024 December 28] Available at: https://urn.nsk.hr/urn:nbn:hr:168:834529

M. Galić, "Sustav za testiranje i verifikaciju brzih sučelja između dva uređaja AMD/Xilinx UltraScale+ FPGA", Master's thesis, University of Zagreb, Faculty of Electrical Engineering and Computing, Zagreb, 2023. Available at: https://urn.nsk.hr/urn:nbn:hr:168:834529

Metadata
TitleSustav za testiranje i verifikaciju brzih sučelja između dva uređaja AMD/Xilinx UltraScale+ FPGA
Title (english)System for test and verification of high speed interfaces between two AMD/Xilinx UltraScale+ FPGA devices
AuthorMirko Galić
MentorAdrijan Barić (mentor)
Committee memberAdrijan Barić (predsjednik povjerenstva)
Committee memberVladimir Čeperić (član povjerenstva)
Committee memberJurica Kundrata (član povjerenstva)
GranterUniversity of Zagreb
Faculty of Electrical Engineering and Computing
Zagreb
Defense date and country2023-06-30, Croatia
Scientific / art field,
discipline and subdiscipline		TECHNICAL SCIENCES
Computing
Abstract
Sve veća potražnja za velikom propusnosti u komunikaciji i što manjoj latenciji dovela je do sve češće upotrebe FPGA tehnologije. Validnost te komunikacije izuzetno je bitan faktor pri nailasku na probleme u razvoju i proizvodnji. U ovom radu razvijena su dva FPGA dizajna međusobno povezana LVDS i GTY sučeljima. Testovi se mogu podijeliti na testove s povratnom petljom za GTY sučelje i na PRBS test za oba sučelja. Oni su prvo implementirani u blok dizajnu i testirani hardverskim putem, a zatim je napisana programska podrška za izvođenje testova na procesoru FPGA. Testovi s povratnom petljom su podizanjem statusnih signala o spremnosti veze potvrdile električnu povezanost dok su PRBS testovi brojem uzoraka i pogrešaka potvrdili kvalitetu i validnost veze.
Abstract (english)
The increasing demand for high bandwith in communication systems and as little latency as possible has led to the increasingly frequent use of FPGA technology. The validity of this communication is an extremely important factor when encountering problems in development and production. In this paper, two FPGA designs interconnected by LVDS and GTY interfaces were developed. The tests can be divided into loopback tests for the GTY interface, and a PRBS test for both interfaces. They were implemented in a block design and tested through hardware, and then software was written for performing tests on the FPGA processor. The loopback tests confirmed the electrical connection and readiness of the connection by raising status signals, while the PRBS tests confirmed the quality and validity of the connection by the number of samples and erorrs transferred.
Keywords
Keywords (english)
Languagecroatian
URN:NBNurn:nbn:hr:168:834529
Study programmeTitle: Computing
Study programme type: university
Study level: graduate
Academic / professional title: magistar/magistra inženjer/inženjerka računarstva (magistar/magistra inženjer/inženjerka računarstva)
Type of resourceText
File originBorn digital
Access conditionsClosed access
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Created on2023-10-11 08:52:46