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doctoral thesis
Relaxation oscillator architectures with delay and offset-voltage compensation
Zagreb: University of Zagreb, Faculty of Electrical Engineering and Computing, 2023. urn:nbn:hr:168:114925
Mikulić, Josip
University of Zagreb
Faculty of Electrical Engineering and Computing

Institutional repository: FER Repository

Cite this document

Mikulić, J. (2023). Relaxation oscillator architectures with delay and offset-voltage compensation (Doctoral thesis). Zagreb: University of Zagreb, Faculty of Electrical Engineering and Computing. Retrieved from https://urn.nsk.hr/urn:nbn:hr:168:114925

Mikulić, Josip. "Relaxation oscillator architectures with delay and offset-voltage compensation." Doctoral thesis, University of Zagreb, Faculty of Electrical Engineering and Computing, 2023. https://urn.nsk.hr/urn:nbn:hr:168:114925

Mikulić, Josip. "Relaxation oscillator architectures with delay and offset-voltage compensation." Doctoral thesis, University of Zagreb, Faculty of Electrical Engineering and Computing, 2023. https://urn.nsk.hr/urn:nbn:hr:168:114925

Mikulić, J. (2023). 'Relaxation oscillator architectures with delay and offset-voltage compensation', Doctoral thesis, University of Zagreb, Faculty of Electrical Engineering and Computing, accessed 26 November 2024, https://urn.nsk.hr/urn:nbn:hr:168:114925

Mikulić J. Relaxation oscillator architectures with delay and offset-voltage compensation [Doctoral thesis]. Zagreb: University of Zagreb, Faculty of Electrical Engineering and Computing; 2023 [cited 2024 November 26] Available at: https://urn.nsk.hr/urn:nbn:hr:168:114925

J. Mikulić, "Relaxation oscillator architectures with delay and offset-voltage compensation", Doctoral thesis, University of Zagreb, Faculty of Electrical Engineering and Computing, Zagreb, 2023. Available at: https://urn.nsk.hr/urn:nbn:hr:168:114925

Metadata
TitleRelaxation oscillator architectures with delay and offset-voltage compensation
Title (croatian)Arhitekture relaksacijskoga oscilatora s kompenzacijom kašnjenja i napona pomaka
AuthorJosip Mikulić
MBZ: 41165
MentorAdrijan Barić (mentor)
Committee memberMarko Koričić (predsjednik povjerenstva)
Committee memberVladimir Čeperić (član povjerenstva)
Committee memberJurica Kundrata (član povjerenstva)
Committee memberGeorges Gielen https://orcid.org/0000-0002-4061-9428 (član povjerenstva)
GranterUniversity of Zagreb
Faculty of Electrical Engineering and Computing
Zagreb
Defense date and country2023-06-05, Croatia
Scientific / art field,
discipline and subdiscipline		TECHNICAL SCIENCES
Electrical Engineering
Universal decimal classification
(UDC)		621.3 - Electrical engineering
Abstract
This thesis presents the detailed theoretical analysis, measurements, and performance comparison of several novel relaxation oscillator architectures, having the main focus on the compensation of the propagation delay and offset voltage of the comparator stage. The first architecture introduces two replica comparators that imitate the behavior of the sensing comparators and compensate for their influence on the timing. Next, a further enhancement of the relaxation oscillator core architecture is proposed, comprising a self–compensating chopped comparator pair that entirely cancels the propagation delay and offset voltage of the comparators while being more efficient in power consumption and area. The third architecture introduces additional integrating unit that is used for measurement and compensation of the propagation delay, being compatible with low supply environments and advanced technology nodes. Furthermore, the fourth relaxation oscillator core architecture comprises replica chopped comparator, providing an efficient delay and offset cancellation with minimal influence on power, area, and signal integrity. Eventually, a cost–efficient methodology for a post–manufacturing temperature calibration that significantly reduces the temperature drift of the output frequency is proposed and demonstrated on a manufactured self–sustaining oscillator prototype.
Abstract (croatian)
Ovaj rad predstavlja detaljnu analizu, mjerenja i usporedbu performansi nekoliko predloženih arhitektura relaksacijskih oscilatora koje su značajno unaprijeđene kompenzacijom kašnjenja i napona pomaka komparatora. Prva predložena arhitektura oscilatora uvodi dva replicirajuća komparatora pomoću kojih se mjeri i kompenzira utjecaj očitavajućih komparatora na stabilnost frekvencije. Nadalje, u drugoj arhitekturi, mjerenje utjecaja komparatora je izvedeno pomoću samokompenzirajućeg preklopnog para komparatora, čime je postignuto dodatno poboljšanje stabilnosti takta uz manju potrošnju struje i površinu na siliciju. Treća predložena arhitektura zasniva se na replicirajućem integratoru te je prikladna za niske napone napajanja i napredne tehnološke procese. Dodatno, četvrta predložena arhitektura jezgre oscilatora temeljena na replicirajućem preklopnom komparatoru donosi dobre performanse uz jednostavnost implementacije i minimalan utjecaj na potrošnju struje i površinu na čipu. Najzad, predložena je metoda temperaturne kalibracije relaksacijskih oscilatora koja se zasniva na mjerenju frekvencije na samo dvije proizvoljne temperature, čime se ograničava porast troškova proizvodnje.
Keywords
Keywords (croatian)
Languageenglish
URN:NBNurn:nbn:hr:168:114925
Promotion2024
Study programmeTitle: Doctoral study programme "Electrical Engineering and Computing"
Study programme type: university
Study level: postgraduate
Academic / professional title: doktor/doktorica znanosti, po-dručje tehničkih znanosti (doktor/doktorica znanosti, po-dručje tehničkih znanosti)
Type of resourceText
Extent181 str. : graf. prikazi ; 31 cm.
File originBorn digital
Access conditionsOpen access
Terms of useLicence In copyright icon
Created on2024-02-13 14:48:28