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master's thesis
Model i izvedba 32-bitnog procesora RISC-V s podrškom za prekide
Zagreb: University of Zagreb, Faculty of Electrical Engineering and Computing, 2024. urn:nbn:hr:168:458292
Grzunov, Matej
University of Zagreb
Faculty of Electrical Engineering and Computing

Institutional repository: FER Repository

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Grzunov, M. (2024). Model i izvedba 32-bitnog procesora RISC-V s podrškom za prekide (Master's thesis). Zagreb: University of Zagreb, Faculty of Electrical Engineering and Computing. Retrieved from https://urn.nsk.hr/urn:nbn:hr:168:458292

Grzunov, Matej. "Model i izvedba 32-bitnog procesora RISC-V s podrškom za prekide." Master's thesis, University of Zagreb, Faculty of Electrical Engineering and Computing, 2024. https://urn.nsk.hr/urn:nbn:hr:168:458292

Grzunov, Matej. "Model i izvedba 32-bitnog procesora RISC-V s podrškom za prekide." Master's thesis, University of Zagreb, Faculty of Electrical Engineering and Computing, 2024. https://urn.nsk.hr/urn:nbn:hr:168:458292

Grzunov, M. (2024). 'Model i izvedba 32-bitnog procesora RISC-V s podrškom za prekide', Master's thesis, University of Zagreb, Faculty of Electrical Engineering and Computing, accessed 26 December 2024, https://urn.nsk.hr/urn:nbn:hr:168:458292

Grzunov M. Model i izvedba 32-bitnog procesora RISC-V s podrškom za prekide [Master's thesis]. Zagreb: University of Zagreb, Faculty of Electrical Engineering and Computing; 2024 [cited 2024 December 26] Available at: https://urn.nsk.hr/urn:nbn:hr:168:458292

M. Grzunov, "Model i izvedba 32-bitnog procesora RISC-V s podrškom za prekide", Master's thesis, University of Zagreb, Faculty of Electrical Engineering and Computing, Zagreb, 2024. Available at: https://urn.nsk.hr/urn:nbn:hr:168:458292

Metadata
TitleModel i izvedba 32-bitnog procesora RISC-V s podrškom za prekide
Title (english)Model and implementation of 32-bit RISC-V processor with support for interrupts
AuthorMatej Grzunov
MentorTomislav Hrkać (mentor)
Committee memberTomislav Hrkać (predsjednik povjerenstva)
Committee memberStjepan Groš (član povjerenstva)
Committee memberNikolina Frid (član povjerenstva)
GranterUniversity of Zagreb
Faculty of Electrical Engineering and Computing
Zagreb
Defense date and country2024-07-02, Croatia
Abstract
Prekidi toka izvođenja temelj su izrade efikasne i robusne programske podrške za ugradbene računalne sustave, jer smanjuju udio radnog čekanja u programima te omogućavaju odgovor na očekivane događaje i neočekivane greške tijekom rada procesora. U ovom diplomskom radu razvijen je RISC-V procesor s podrškom za prekide toka izvođenja i RISC-V naprednu prekidnu arhitekturu. Izvedeni procesor sadrži jednu procesorsku jezgru s klasičnom RISC protočnom strukturom s 5 protočnih razina, rudimentarnu memoriju, te ulazno/izlazne jedinice za komunikaciju s vanjskim svijetom. Procesor je opisan SystemVerilog jezikom, sintetiziran i izveden za FPGA čip, te programiran i upogonjen na ULX3S razvojnoj pločici.
Abstract (english)
Execution flow interrupts are the basis of efficient and robust embedded systems’ software because they reduce the share of the time spent in a program loop waiting for input/output operations to finish. They also enable a processor to respond to expected events and unexpected errors during runtime. As part of this thesis, a RISC-V processor that supports execution flow interrupts was developed, implementing the RISC-V advanced interrupt architecture. Its single processor core includes the classic RISC 5-stage pipeline. The developed processor also includes a rudimentary memory implementation, and input/output units it can use to communicate with the outside world. The processor was described using SystemVerilog, synthesized, and implemented for an FPGA chip. After programming it was run on the ULX3S development board.
Keywords
Keywords (english)
Languagecroatian
URN:NBNurn:nbn:hr:168:458292
Study programmeTitle: Computing
Study programme type: university
Study level: graduate
Academic / professional title: magistar/magistra inženjer/inženjerka računarstva (magistar/magistra inženjer/inženjerka računarstva)
Type of resourceText
File originBorn digital
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Created on2024-10-12 20:45:00