prikaz prve stranice dokumenta Izgradnja sintetizatora pojednostavljenog VHDL-modela za GAL16v8
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master's thesis
Izgradnja sintetizatora pojednostavljenog VHDL-modela za GAL16v8
Zagreb: University of Zagreb, Faculty of Electrical Engineering and Computing, 2017. urn:nbn:hr:168:228798
Munjas, Deni
University of Zagreb
Faculty of Electrical Engineering and Computing

Institutional repository: FER Repository

Cite this document

Munjas, D. (2017). Izgradnja sintetizatora pojednostavljenog VHDL-modela za GAL16v8 (Master's thesis). Zagreb: University of Zagreb, Faculty of Electrical Engineering and Computing. Retrieved from https://urn.nsk.hr/urn:nbn:hr:168:228798

Munjas, Deni. "Izgradnja sintetizatora pojednostavljenog VHDL-modela za GAL16v8." Master's thesis, University of Zagreb, Faculty of Electrical Engineering and Computing, 2017. https://urn.nsk.hr/urn:nbn:hr:168:228798

Munjas, Deni. "Izgradnja sintetizatora pojednostavljenog VHDL-modela za GAL16v8." Master's thesis, University of Zagreb, Faculty of Electrical Engineering and Computing, 2017. https://urn.nsk.hr/urn:nbn:hr:168:228798

Munjas, D. (2017). 'Izgradnja sintetizatora pojednostavljenog VHDL-modela za GAL16v8', Master's thesis, University of Zagreb, Faculty of Electrical Engineering and Computing, accessed 28 December 2024, https://urn.nsk.hr/urn:nbn:hr:168:228798

Munjas D. Izgradnja sintetizatora pojednostavljenog VHDL-modela za GAL16v8 [Master's thesis]. Zagreb: University of Zagreb, Faculty of Electrical Engineering and Computing; 2017 [cited 2024 December 28] Available at: https://urn.nsk.hr/urn:nbn:hr:168:228798

D. Munjas, "Izgradnja sintetizatora pojednostavljenog VHDL-modela za GAL16v8", Master's thesis, University of Zagreb, Faculty of Electrical Engineering and Computing, Zagreb, 2017. Available at: https://urn.nsk.hr/urn:nbn:hr:168:228798

Metadata
TitleIzgradnja sintetizatora pojednostavljenog VHDL-modela za GAL16v8
Title (english)Synthesizer of Simplified VHDL-Based Model for GAL16v8
AuthorDeni Munjas
MentorMarko Čupić (mentor)
Committee memberMarko Čupić (predsjednik povjerenstva)
Committee memberMarin Golub (član povjerenstva)
Committee memberLeonardo Jelenković (član povjerenstva)
GranterUniversity of Zagreb
Faculty of Electrical Engineering and Computing
Zagreb
Defense date and country2017-09-28, Croatia
Scientific / art field,
discipline and subdiscipline		TECHNICAL SCIENCES
Computing
Abstract
Projektiranje te minimizacija digitalnih sklopova su tema s kojom se studenti fakulteta elektrotehnike i računarstva susreću već na prvoj godini studija. U nadi da im se olakša shvaćanje ovog gradiva implementiran je sintetizator pojednostavljenog VHDL-modela za programabilni čip GAL16v8. Program će studentima omogućiti da svoj sklop opišu formalnim jezikom VHDL te da ga pomoću sintetizatora programiraju u GAL16v8. Uz sintetizator, implementiran je i heuristički minimizacijski algoritam Espresso koji pruža niz efikasnih operacija za manipulaciju Booleovih funkcija.
Abstract (english)
Designing and minimizing digital circuits are topics that students of electrical engineering and computing learn already in their first year of study. In the hope of making it easier to understand this material, a synthesizer of the simplified VHDL-based model for GAL16v8 was implemented. The program will allow students to describe their circuit in a formal VHDL language and program it using a synthesizer for GAL16v8. Along with the synthesizer, a heuristic minimization algorithm Espresso has been implemented, which provides a series of efficient operations to manipulate Boolean functions.
Keywords
Keywords (english)
Languagecroatian
URN:NBNurn:nbn:hr:168:228798
Study programmeTitle: Computing
Study programme type: university
Study level: graduate
Academic / professional title: magistar/magistra inženjer/inženjerka računarstva (magistar/magistra inženjer/inženjerka računarstva)
Type of resourceText
File originBorn digital
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Created on2019-03-13 23:18:13