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master's thesis
Dizajn i FPGA implementacija nerekurzivnog poboljšanog CIC filtra bez množila
Zagreb: University of Zagreb, Faculty of Electrical Engineering and Computing, 2019. urn:nbn:hr:168:062764
Knežević, Marija
University of Zagreb
Faculty of Electrical Engineering and Computing

Institutional repository: FER Repository

Cite this document

Knežević, M. (2019). Dizajn i FPGA implementacija nerekurzivnog poboljšanog CIC filtra bez množila (Master's thesis). Zagreb: University of Zagreb, Faculty of Electrical Engineering and Computing. Retrieved from https://urn.nsk.hr/urn:nbn:hr:168:062764

Knežević, Marija. "Dizajn i FPGA implementacija nerekurzivnog poboljšanog CIC filtra bez množila." Master's thesis, University of Zagreb, Faculty of Electrical Engineering and Computing, 2019. https://urn.nsk.hr/urn:nbn:hr:168:062764

Knežević, Marija. "Dizajn i FPGA implementacija nerekurzivnog poboljšanog CIC filtra bez množila." Master's thesis, University of Zagreb, Faculty of Electrical Engineering and Computing, 2019. https://urn.nsk.hr/urn:nbn:hr:168:062764

Knežević, M. (2019). 'Dizajn i FPGA implementacija nerekurzivnog poboljšanog CIC filtra bez množila', Master's thesis, University of Zagreb, Faculty of Electrical Engineering and Computing, accessed 27 December 2024, https://urn.nsk.hr/urn:nbn:hr:168:062764

Knežević M. Dizajn i FPGA implementacija nerekurzivnog poboljšanog CIC filtra bez množila [Master's thesis]. Zagreb: University of Zagreb, Faculty of Electrical Engineering and Computing; 2019 [cited 2024 December 27] Available at: https://urn.nsk.hr/urn:nbn:hr:168:062764

M. Knežević, "Dizajn i FPGA implementacija nerekurzivnog poboljšanog CIC filtra bez množila", Master's thesis, University of Zagreb, Faculty of Electrical Engineering and Computing, Zagreb, 2019. Available at: https://urn.nsk.hr/urn:nbn:hr:168:062764

Metadata
TitleDizajn i FPGA implementacija nerekurzivnog poboljšanog CIC filtra bez množila
Title (english)Design and Multiplierless FPGA Implementation of Non-Recursive Improved CIC Filter
AuthorMarija Knežević
MentorDavor Petrinović (mentor)
Committee memberDavor Petrinović (predsjednik povjerenstva)
Committee memberMladen Vučić (član povjerenstva)
Committee memberGoran Molnar (član povjerenstva)
GranterUniversity of Zagreb
Faculty of Electrical Engineering and Computing
Zagreb
Defense date and country2019-07-11, Croatia
Scientific / art field,
discipline and subdiscipline		TECHNICAL SCIENCES
Computing
Scientific / art field,
discipline and subdiscipline		TECHNICAL SCIENCES
Electrical Engineering
Abstract
U radu su proučeni postupci dizajna i realizacije filtara s konačnim impulsnim odzivom (FIR) koji proizlaze iz različitih tehnika poboljšanja amplitudne karakteristike CIC filtra. Posebno su proučeni postupci koji rezultiraju prijenosnim funkcijama niskog reda i imaju cjelobrojne koeficijente. Takve prijenosne funkcije mogu se učinkovito realizirati nerekurzivnim strukturama koje ne sadrže množila. Svaki cjelobrojni koeficijent zapisan je kao suma potencija broja dva, a zatim je iz sume pronađena optimalna realizacija odnosno ona koja sadrži najmanji broj zbrajala. Optimalna realizacija za svaki pojedini koeficijent pronađena je primjenom iscrpnog pretraživanja nad skupom direktnih acikličkih grafova. Razvijen je fizički ostvariv model filtra koji ima direktnu realizaciju. Model je razvijen u jeziku VHDL te optimiziran za implementaciju na programabilnim logičkim poljima (FPGA). Razvijeno je odgovarajuće ispitno okruženje, provedena simulacija te je model uhodan na stvarnom sklopovlju.
Abstract (english)
In the thesis, the design and implementation of the finite impluse response filters (FIRs) based on amplitude improvements of the CIC filters, was studied. Particulary were considered techniques that result in low-order transfer functions and have integer coefficients. Such transfer functions can be efficiently realized with non-recusrive structures that do not employ general purpose multipliers. Each integer coefficient was represented as sum of power of two. Optimal coefficient realization, with lowest number of adders, was obtained by applying exhaustive search over the set of directed acyclic graphs (DAGs). Register transfer level (RTL) model has been developed in VHDL langugage and optimized for development in programmable logic fields (FPGAs). An appropriate test environment was developed, simuation was carried out, and the model was implemented on real hardware.
Keywords
Keywords (english)
Languagecroatian
URN:NBNurn:nbn:hr:168:062764
Study programmeTitle: Electrical Engineering and Information Technology
Study programme type: university
Study level: graduate
Academic / professional title: magistar/magistra inženjer/inženjerka elektrotehnike i informacijske tehnologije (magistar/magistra inženjer/inženjerka elektrotehnike i informacijske tehnologije)
Type of resourceText
File originBorn digital
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Created on2020-01-07 19:09:35