prikaz prve stranice dokumenta Implementacija jednostavnog procesora u FPGA-u
No public access
undergraduate thesis
Implementacija jednostavnog procesora u FPGA-u
Zagreb: University of Zagreb, Faculty of Electrical Engineering and Computing, 2021. urn:nbn:hr:168:887722
Harmina, Tomislav
University of Zagreb
Faculty of Electrical Engineering and Computing

Institutional repository: FER Repository

Cite this document

Harmina, T. (2021). Implementacija jednostavnog procesora u FPGA-u (Undergraduate thesis). Zagreb: University of Zagreb, Faculty of Electrical Engineering and Computing. Retrieved from https://urn.nsk.hr/urn:nbn:hr:168:887722

Harmina, Tomislav. "Implementacija jednostavnog procesora u FPGA-u." Undergraduate thesis, University of Zagreb, Faculty of Electrical Engineering and Computing, 2021. https://urn.nsk.hr/urn:nbn:hr:168:887722

Harmina, Tomislav. "Implementacija jednostavnog procesora u FPGA-u." Undergraduate thesis, University of Zagreb, Faculty of Electrical Engineering and Computing, 2021. https://urn.nsk.hr/urn:nbn:hr:168:887722

Harmina, T. (2021). 'Implementacija jednostavnog procesora u FPGA-u', Undergraduate thesis, University of Zagreb, Faculty of Electrical Engineering and Computing, accessed 27 December 2024, https://urn.nsk.hr/urn:nbn:hr:168:887722

Harmina T. Implementacija jednostavnog procesora u FPGA-u [Undergraduate thesis]. Zagreb: University of Zagreb, Faculty of Electrical Engineering and Computing; 2021 [cited 2024 December 27] Available at: https://urn.nsk.hr/urn:nbn:hr:168:887722

T. Harmina, "Implementacija jednostavnog procesora u FPGA-u", Undergraduate thesis, University of Zagreb, Faculty of Electrical Engineering and Computing, Zagreb, 2021. Available at: https://urn.nsk.hr/urn:nbn:hr:168:887722

Metadata
TitleImplementacija jednostavnog procesora u FPGA-u
Title (english)FPGA Implementation of a Simple Processor
AuthorTomislav Harmina
MentorDaniel Hofman (mentor)
Committee memberDaniel Hofman (predsjednik povjerenstva)
Committee memberAlen Duspara (član povjerenstva)
Committee memberLuka Macan (član povjerenstva)
GranterUniversity of Zagreb
Faculty of Electrical Engineering and Computing
Zagreb
Defense date and country2021-07-01, Croatia
Scientific / art field,
discipline and subdiscipline		TECHNICAL SCIENCES
Computing
Abstract
U ovom radu napravljena je jednostavna implementacija protočnog RISC-V procesora baziranog na RV32I arhitekturi. Za implementaciju korišten je jezik VHDL i Xilinx Vivado WebPack razvojno sučelje. Procesor je testiran koristeći razvojnu platformu Digilent Nexys A7. Procesoru je radi testiranja na razvojnoj platformi dodan i sabirnički upravljač. Opisane su i vanjske jedinice koje procesor povezuju s uređajima na razvojnoj platformi. Za ispitivanje procesora razvijena su i objašnjena tri jednostavna programa. Za kraj analizirane su performanse procesora i dane su preporuke za njegov daljnji razvoj.
Abstract (english)
This thesis describes the implementation of a simple pipelined RISC-V processor based on the RV32I instruction set architecture. The processor was implemented using VHDL and Xilinx Vivado WebPack software suite. Tests were done on a Digilent Nexys A7 development board. The processor also contains a simple bus controller to enable the processor to interface with development board's devices. For the purposes of testing three programs have been developed and explained. Finally, the processors performance has been analyzed and some ideas for improving the processors performance have been given.
Keywords
Keywords (english)
Languagecroatian
URN:NBNurn:nbn:hr:168:887722
Study programmeTitle: Computing
Study programme type: university
Study level: undergraduate
Academic / professional title: sveučilišni/a prvostupnik/ prvostupnica (baccalaureus/baccalaurea) inženjer/inženjerka računarstva (sveučilišni/a prvostupnik/ prvostupnica (baccalaureus/baccalaurea) inženjer/inženjerka računarstva)
Type of resourceText
File originBorn digital
Access conditionsClosed access
Terms of useLicence In copyright icon
Public note
Created on2023-01-14 20:33:24