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undergraduate thesis
Prikaz rezultata Verilog simulacije u LaTeX dokumentu
Split: University of Split, Faculty of Electrical Engineering, Mechanical Engineering and Naval Architecture, 2021. urn:nbn:hr:179:095172
Majić, Danica
University of Split
Faculty of Electrical Engineering, Mechanical Engineering and Naval Architecture
Department of Electronics and Computing

Institutional repository: Repository of the Faculty of Electrical Engineering, Mechanical Engineering and Naval Architecture

Cite this document

Majić, D. (2021). Prikaz rezultata Verilog simulacije u LaTeX dokumentu (Undergraduate thesis). Split: University of Split, Faculty of Electrical Engineering, Mechanical Engineering and Naval Architecture. Retrieved from https://urn.nsk.hr/urn:nbn:hr:179:095172

Majić, Danica. "Prikaz rezultata Verilog simulacije u LaTeX dokumentu." Undergraduate thesis, University of Split, Faculty of Electrical Engineering, Mechanical Engineering and Naval Architecture, 2021. https://urn.nsk.hr/urn:nbn:hr:179:095172

Majić, Danica. "Prikaz rezultata Verilog simulacije u LaTeX dokumentu." Undergraduate thesis, University of Split, Faculty of Electrical Engineering, Mechanical Engineering and Naval Architecture, 2021. https://urn.nsk.hr/urn:nbn:hr:179:095172

Majić, D. (2021). 'Prikaz rezultata Verilog simulacije u LaTeX dokumentu', Undergraduate thesis, University of Split, Faculty of Electrical Engineering, Mechanical Engineering and Naval Architecture, accessed 28 December 2024, https://urn.nsk.hr/urn:nbn:hr:179:095172

Majić D. Prikaz rezultata Verilog simulacije u LaTeX dokumentu [Undergraduate thesis]. Split: University of Split, Faculty of Electrical Engineering, Mechanical Engineering and Naval Architecture; 2021 [cited 2024 December 28] Available at: https://urn.nsk.hr/urn:nbn:hr:179:095172

D. Majić, "Prikaz rezultata Verilog simulacije u LaTeX dokumentu", Undergraduate thesis, University of Split, Faculty of Electrical Engineering, Mechanical Engineering and Naval Architecture, Split, 2021. Available at: https://urn.nsk.hr/urn:nbn:hr:179:095172

Metadata
TitlePrikaz rezultata Verilog simulacije u LaTeX dokumentu
Title (english)Presentation of Verilog simulation results in LaTeX document
AuthorDanica Majić
MentorDuje Čoko (mentor)
GranterUniversity of Split
Faculty of Electrical Engineering, Mechanical Engineering and Naval Architecture
(Department of Electronics and Computing)
Split
Defense date and country2021-09-23, Croatia
Scientific / art field,
discipline and subdiscipline		TECHNICAL SCIENCES
Electrical Engineering
Electronics
Abstract
Verilog HDL je jedan od nakorištenijih HDL jezika za modeliranje i simuliranje sklopova. Razvoj tehnologije u modernom dobu utjecao je na složenost sklopova koji se koriste, a Verilog HDL omogućuje simuliranje i testiranje sklopova različite skloženosti prije konstrukcije dizajna. Testiranjem dizajna prije njegove implementacije povećava ekonomičnost proizvodnje sklopova jer se moguće pogreške mogu unaprijed ispraviti. VCD datoteke koje su rezultat simulacije Verilog modula omogućuju korisnicima praćenje stanja i modifikacije varijabli unutar modula. VCD datoteke korisne su za grafički prikaz promjena stanja varijabli pošto se mogu očitavati nizom softverskih alata, jedan od kojih je GTKWave. LaTeX softver za pripremu dokumenata pruža profesionalni izgled napisanog dokumenta. Samostalno specificira strukturu dokumenta, a njegova najveća prednost je što jednako radi na svim platformama. Tikz-timing paket omogu- ćuje kreiranje svih vrsta vremenskih dijagrama predefiniranim vrijednostima signala, razinama za visoko i nisko logičko stanje i svim kombinacijama prijelaza između tih stanja.
Abstract (english)
Verilog HDL is one of the most widely used HDL languages for circuit modeling and simulation. The development of technology in the modern ages has affected the complexity of hardware and Verilog HDL allows the simulation and testing of hardware of different complexity before the construction of the design. Testing the design before its implementation increases the cost-effectiveness of manufacturing the hardware because possible errors can be corrected in advance. VCD files resulting from the Verilog module simulation allow users to monitor and modify the state of variables within the module. VCD files are useful for graphically displaying changes in the state of variables as they can be read by various software tools, one of which is GTKWave. LaTeX document preparation software provides a professional format to the written document. It independently specifies the structure of the document and its biggest advantage is working equally on all platforms. The tikz-timing package allows the creation of all types of timing diagrams with predefined signal values, levels for high and low logic states and all combinations of transitions between these states.
Keywords
Keywords (english)
Languagecroatian
URN:NBNurn:nbn:hr:179:095172
Study programmeTitle: Electrical Engineering and Information Technology
Study programme type: university
Study level: undergraduate
Academic / professional title: sveučilišni/a prvostupnik/ prvostupnica (baccalaureus/baccalaurea) inženjer/inženjerka elektrotehnike i informacijske tehnologije (sveučilišni/a prvostupnik/ prvostupnica (baccalaureus/baccalaurea) inženjer/inženjerka elektrotehnike i informacijske tehnologije)
Type of resourceText
File originBorn digital
Access conditionsAccess restricted to students and staff of home institution
Terms of useLicence In copyright icon
Created on2021-12-07 13:01:01