This thesis is focused on designing frequency divider (FDIV) and phase-frequency detector (PFD). Both circuits are part of a circuit called phase-locked loop (PLL). PLL also contains other circuits which are: charge pump, lowpass filter, voltage controlled oscillator, level shifter and duty-cycle control. Generating stable output frequency is the main purpose of a PLL. Its input signal must have a stable frequency of f_{REF} = 2 MHz. The output frequency is f_{REF} = 20 MHz. FDIV is located in the negative feedback where the output frequency f_{VCO} is divided by 10 and becomes f_{FDIV} = 2 MHz. FDIV is a synchronous divider and consists of D flip-flops. The division of the output frequency takes place in two stages: first by 2 and then by 5. The output signal from FDIV is afterwards compared with the reference signal FREF in the PFD. The PFD produces an error signal which controls the charge pump. If the signal FDIV precedes the signal FREF, PFD will generate wider $dwn$ pulses. The charge pump will thus discharge the capacitor located in the lowpass filter and both the control voltage V_{CTRL} and the output frequency f_{VCO} will drop. This results in a smaller phase difference between input signals FDIV and FREF. Conversely, if the input signal FREF precedes the signal FDIV, up pulses will be wider, so the capacitor is being charged, which means that the output frequency rises. All circuits in the PLL have a pd (power down) signal. When this signal is in high state, all circuits stop working, i.e. consumption current is 2,7 times smaller than normal for FDIV and 6,58 times smaller for PFD. The fuctionality of the circuits PFD and FDIV needs to be tested in minimum, nominal and maximum working conditions. That includes simulations for different values of temperature and supply voltage, because output signals should not have a too long delay time. After the design process, top level simulations of the whole PLL are performed.