In the last several years, the most difficult problem in nanoelectronics is the management of the heat generated during information processing which resulted in the processor operational frequency stagnation. The source of that problem lies in the fundamental physics of the transistors, key semiconductor component in modern electronic devices. Although transistor sizes reduced to the nanometer scale since their invention in 1947, today market requires their further reduction. But the ongoing scaling will be eventually limited by the inability to remove the heat generated in the switching process. Reducing transistor’s operational voltage would provide elimination of the mentioned problem which would also speed up electronic devices. Negative electrical capacitance has emerged as a solution which provides reduction of operational voltage below standard value (∼ 1 V). Combination of ferroelectric material and linear dielectric at the gate region of FET would effectively behave like series combination of two capacitors, of which one has negative capacitance. The main goal of this thesis is to show why does negative capacitance emerges in ferroelectrics, is there a possibility to access this region and under what conditions, and finally what are the consequences of negative capacitance on the transistors.